@@ -314,3 +314,3 @@ build_prepend_package_length(GArray *package, unsigned length, bool incl_self)
* and PkgLength's length itself when used for terms with
- * explitit length.
+ * explicit length.
*/
@@ -682,3 +682,3 @@ Aml *aml_store(Aml *val, Aml *target)
*
- * Returns: The newly allocated and composed according to patter Aml object.
+ * Returns: The newly allocated and composed according to pattern Aml object.
*/
@@ -2161,3 +2161,3 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
} else {
- build_append_int_noprefix(tbl, 0, 3); /* Reserved upto ACPI 5.0 */
+ build_append_int_noprefix(tbl, 0, 3); /* Reserved up to ACPI 5.0 */
}
@@ -84,3 +84,3 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb,
uint32_t lb_length
- = 32 /* Table length upto and including Entry Base Unit */
+ = 32 /* Table length up to and including Entry Base Unit */
+ 4 * num_initiator /* Initiator Proximity Domain List */
@@ -1099,3 +1099,3 @@ static void nvdimm_build_common_dsm(Aml *dev,
* size is 32 bits, otherwise it is 64 bits.
- * Because of this CreateField() canot be used if RLEN < Integer Size.
+ * Because of this CreateField() cannot be used if RLEN < Integer Size.
*
@@ -52,3 +52,3 @@ struct partition {
-/* try to guess the disk logical geometry from the MSDOS partition table.
+/* try to guess the disk logical geometry from the MS-DOS partition table.
Return 0 if OK, -1 if could not guess */
@@ -68,3 +68,3 @@ static int guess_disk_lchs(BlockBackend *blk,
}
- /* test msdos magic */
+ /* test MS-DOS magic */
if (buf[510] != 0x55 || buf[511] != 0xaa) {
@@ -893,3 +893,3 @@ static Property pflash_cfi01_properties[] = {
* If we're emulating flash devices wired in parallel the actual
- * number of blocks per indvidual device will differ.
+ * number of blocks per individual device will differ.
*/
@@ -577,3 +577,3 @@ static int cadence_uart_pre_load(void *opaque)
- /* the frequency will be overriden if the refclk field is present */
+ /* the frequency will be overridden if the refclk field is present */
clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
@@ -114,3 +114,3 @@ static void imx_serial_reset_at_boot(DeviceState *dev)
/*
- * enable the uart on boot, so messages from the linux decompresser
+ * enable the uart on boot, so messages from the linux decompressor
* are visible. On real hardware this is done by the boot rom
@@ -56,3 +56,3 @@
-#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
+#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functioning */
#define UART_IIR_FE 0xC0 /* Fifo enabled */
@@ -26,3 +26,3 @@
* This device allows the user to monkey patch memory. To be able to do
- * this it needs a backend to manage the datas, the same as other
+ * this it needs a backend to manage the data, the same as other
* memory-related devices. In this case as the backend is so trivial we
@@ -168,3 +168,3 @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
- /* Convert the data endiannes */
+ /* Convert the data endianness */
if (s->data_be) {
@@ -865,3 +865,3 @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
* The Linux header magic number for a EFI PE/COFF
- * image targetting an unspecified architecture.
+ * image targeting an unspecified architecture.
*/
@@ -1494,3 +1494,3 @@ RomGap rom_find_largest_gap_between(hwaddr base, size_t size)
}
- /* ignore anything finishing bellow base */
+ /* ignore anything finishing below base */
if (rom->addr + rom->romsize <= base) {
@@ -1416,3 +1416,3 @@ void machine_run_board_init(MachineState *machine, const char *mem_path, Error *
machine_class->valid_cpu_types[i])) {
- /* The user specificed CPU is in the valid field, we are
+ /* The user specified CPU is in the valid field, we are
* good to go.
@@ -109,3 +109,3 @@ static void set_drive_helper(Object *obj, Visitor *v, const char *name,
if (*ptr) {
- /* BlockBackend alread exists. So, we want to change attached node */
+ /* BlockBackend already exists. So, we want to change attached node */
blk = *ptr;
@@ -163,3 +163,3 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, a15mp_priv_properties);
- /* We currently have no savable state */
+ /* We currently have no saveable state */
}
@@ -199,3 +199,3 @@ CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds, CXLClearEventPayload *
/*
- * Must itterate the queue twice.
+ * Must iterate the queue twice.
* "The device shall verify the event record handles specified in the input
@@ -41,3 +41,3 @@
*
- * XXX: The handler need not worry about endianess. The payload is read out of
+ * XXX: The handler need not worry about endianness. The payload is read out of
* a register interface that already deals with it.
@@ -503,3 +503,3 @@ static CXLRetCode cmd_media_get_poison_list(struct cxl_cmd *cmd,
query_start = ldq_le_p(&in->pa);
- /* 64 byte alignemnt required */
+ /* 64 byte alignment required */
if (query_start & 0x3f) {
@@ -249,3 +249,3 @@ static void omap_dma_deactivate_channel(struct omap_dma_s *s,
- /* Don't deactive the channel if it is synchronized and the DMA request is
+ /* Don't deactivate the channel if it is synchronized and the DMA request is
active */
@@ -424,3 +424,3 @@ static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
a->pck_element ++;
- /* Check if a full packet has beed transferred. */
+ /* Check if a full packet has been transferred. */
if (a->pck_element == a->pck_elements) {
@@ -211,3 +211,3 @@ static void hid_pointer_sync(DeviceState *dev)
} else {
- /* prepate next (clear rel, copy abs + btns) */
+ /* prepare next (clear rel, copy abs + btns) */
if (hs->kind == HID_MOUSE) {
@@ -159,10 +159,10 @@ static uint16_t tsc2005_read(TSC2005State *s, int reg)
- case 0x8: /* AUX high treshold */
+ case 0x8: /* AUX high threshold */
return s->aux_thr[1];
- case 0x9: /* AUX low treshold */
+ case 0x9: /* AUX low threshold */
return s->aux_thr[0];
- case 0xa: /* TEMP high treshold */
+ case 0xa: /* TEMP high threshold */
return s->temp_thr[1];
- case 0xb: /* TEMP low treshold */
+ case 0xb: /* TEMP low threshold */
return s->temp_thr[0];
@@ -188,6 +188,6 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
switch (reg) {
- case 0x8: /* AUX high treshold */
+ case 0x8: /* AUX high threshold */
s->aux_thr[1] = data;
break;
- case 0x9: /* AUX low treshold */
+ case 0x9: /* AUX low threshold */
s->aux_thr[0] = data;
@@ -195,6 +195,6 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
- case 0xa: /* TEMP high treshold */
+ case 0xa: /* TEMP high threshold */
s->temp_thr[1] = data;
break;
- case 0xb: /* TEMP low treshold */
+ case 0xb: /* TEMP low threshold */
s->temp_thr[0] = data;
@@ -193,3 +193,3 @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
s->coreisr[cpu][index] = old_data & ~val;
- /* write 1 to clear interrrupt */
+ /* write 1 to clear interrupt */
old_data &= val;
@@ -1,3 +1,3 @@
/*
- * QEMU Loongson Local I/O interrupt controler.
+ * QEMU Loongson Local I/O interrupt controller.
*
@@ -70,3 +70,3 @@ static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
/* Find the interrupt line with the highest dynamic priority.
- * Note: 0 denotes the hightest priority.
+ * Note: 0 denotes the highest priority.
* If all interrupts have the same priority, the default order is IRQ_N,
@@ -945,3 +945,3 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
/*
- * Configure store EOI if required by firwmare (skiboot has removed
+ * Configure store EOI if required by firmware (skiboot has removed
* support recently though)
@@ -29,3 +29,3 @@
/*
- * XIVE Virtualization Controller BAR and Thread Managment BAR that we
+ * XIVE Virtualization Controller BAR and Thread Management BAR that we
* use for the ESB pages and the TIMA pages
@@ -487,3 +487,3 @@ static int kvmppc_xive_get_queues(SpaprXive *xive, Error **errp)
* PQs to PENDING to stop the flow of events and to possibly catch a
- * triggered interrupt occuring while the VM is stopped. The previous
+ * triggered interrupt occurring while the VM is stopped. The previous
* state is saved in anticipation of a migration. The XIVE controller
@@ -553,3 +553,3 @@ static void kvmppc_xive_change_state_handler(void *opaque, bool running,
* PQ is set to PENDING to possibly catch a triggered
- * interrupt occuring while the VM is stopped (hotplug event
+ * interrupt occurring while the VM is stopped (hotplug event
* for instance) .
@@ -635,3 +635,3 @@ int kvmppc_xive_post_load(SpaprXive *xive, int version_id)
- /* Restore the ENDT first. The targetting depends on it. */
+ /* Restore the ENDT first. The targeting depends on it. */
for (i = 0; i < xive->nr_ends; i++) {
@@ -1603,3 +1603,3 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
* matching NVT (or more) dispatched on the processor threads. In case
- * of a single NVT notification, the process is abreviated and the
+ * of a single NVT notification, the process is abbreviated and the
* thread is signaled if a match is found. In case of a logical server
@@ -544,3 +544,3 @@ static void xive2_router_realize(DeviceState *dev, Error **errp)
* Notification using the END ESe/ESn bit (Event State Buffer for
- * escalation and notification). Profide futher coalescing in the
+ * escalation and notification). Profide further coalescing in the
* Router.
@@ -623,3 +623,3 @@ static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
* Check the END ESn (Event State Buffer for notification) for
- * even futher coalescing in the Router
+ * even further coalescing in the Router
*/
@@ -704,3 +704,3 @@ do_escalation:
* Check the END ESe (Event State Buffer for escalation) for even
- * futher coalescing in the Router
+ * further coalescing in the Router
*/
@@ -303,3 +303,3 @@ static void handle_msg(IPMIBmcExtern *ibe)
} else {
- ibe->inpos--; /* Remove checkum */
+ ibe->inpos--; /* Remove checksum */
}
@@ -540,3 +540,3 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
/*
- * If no more errors, then follow recomendation of PCI spec
+ * If no more errors, then follow recommendation of PCI spec
* r6.0 6.2.4.2 to set the first error pointer to a status
@@ -699,3 +699,3 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
- /* MSI(-X) Initailization */
+ /* MSI(-X) Initialization */
rc = msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL);
@@ -708,3 +708,3 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
- /* DOE Initailization */
+ /* DOE Initialization */
pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0);
@@ -229,3 +229,3 @@ static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
* timer can have its own clock root.
- * This means we need additionnal information when calling this
+ * This means we need additional information when calling this
* function to know the requester's identity.
@@ -248,3 +248,3 @@
#define vSR 0x1400 /* [VIA only] Shift register. */
-#define vACR 0x1600 /* [VIA only] Auxilary control register. */
+#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
@@ -96,3 +96,3 @@ static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
qemu_log_mask(LOG_UNIMP,
- "%s: Changeing the memory mapping isn't supported " \
+ "%s: Changing the memory mapping isn't supported " \
"in QEMU\n", __func__);
@@ -101,3 +101,3 @@ static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
qemu_log_mask(LOG_UNIMP,
- "%s: Changeing the memory mapping isn't supported " \
+ "%s: Changing the memory mapping isn't supported " \
"in QEMU\n", __func__);
@@ -157,3 +157,3 @@ stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx
# stm32f4xx_exti.c
-stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
+stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
@@ -287,3 +287,3 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk)
/**
- * Compute and set the ouputs clocks periods.
+ * Compute and set the outputs clocks periods.
* But do not propagate them further. Connected clocks
@@ -19,3 +19,3 @@
* While QEMU coding style prefers lowercase hexadecimals in constants, the
- * NVMe subsystem use thes format from the NVMe specifications in the comments
+ * NVMe subsystem use this format from the NVMe specifications in the comments
* (i.e. 'h' suffix instead of '0x' prefix).
@@ -732,3 +732,3 @@ static inline void nvme_sg_unmap(NvmeSg *sg)
/*
- * When metadata is transfered as extended LBAs, the DPTR mapped into `sg`
+ * When metadata is transferred as extended LBAs, the DPTR mapped into `sg`
* holds both data and metadata. This function splits the data and metadata
@@ -7615,3 +7615,3 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
* an invalid value to the Submission Queue Tail Doorbell or
- * Completion Queue Head Doorbell regiter and an Asynchronous Event
+ * Completion Queue Head Doorbell register and an Asynchronous Event
* Request command is outstanding, then an asynchronous event is
@@ -53,3 +53,3 @@ struct EEPROMState {
bool changed;
- /* during WRITE, # of address bytes transfered */
+ /* during WRITE, # of address bytes transferred */
uint8_t haveaddr;
@@ -879,3 +879,3 @@ static struct {
* as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
- * In order to avoid the inconsistency in sizes save them seperately and
+ * In order to avoid the inconsistency in sizes save them separately and
* migrate over in vmstate post_load().
@@ -204,3 +204,3 @@ static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
freq = s->freq;
- /* set frequncy for time generator */
+ /* set frequency for time generator */
s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
@@ -116,3 +116,3 @@ static const uint8_t ipr_table[NR_IRQS] = {
/*
- * Level triggerd IRQ list
+ * Level triggered IRQ list
* Not listed IRQ is Edge trigger.
@@ -1323,3 +1323,3 @@ again:
insn & (1 << 3) ? " ATN" : "");
- /* ??? Linux drivers compain when this is set. Maybe
+ /* ??? Linux drivers complain when this is set. Maybe
it only applies in low-level mode (unimplemented).
@@ -67,3 +67,3 @@
#define MFI_SEQ 0xfc /* Sequencer offset */
-#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */
+#define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */
#define MFI_RMI 0x2 /* reply message interrupt */
@@ -1226,3 +1226,3 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
- /* Block read commands (Classs 2) */
+ /* Block read commands (Class 2) */
case 16: /* CMD16: SET_BLOCKLEN */
@@ -1807,3 +1807,3 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
* We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
- * here becuase it will result in a call to
+ * here because it will result in a call to
* sdhci_send_command(s) which we don't want.
@@ -103,3 +103,3 @@ static void isl_pmbus_vr_exit_reset(Object *obj)
-/* The raa228000 uses different direct mode coefficents from most isl devices */
+/* The raa228000 uses different direct mode coefficients from most isl devices */
static void raa228000_exit_reset(Object *obj)
@@ -736,3 +736,3 @@ static void max34451_init(Object *obj)
* get and set the temperature of the internal temperature sensor in
- * centidegrees Celcius i.e.: 2500 -> 25.00 C, max is 327.67 C
+ * centidegrees Celsius i.e.: 2500 -> 25.00 C, max is 327.67 C
*/
@@ -115,3 +115,3 @@
-/* TLB exeption address register - TEA */
+/* TLB exception address register - TEA */
#define SH7750_TEA_REGOFS 0x00000c /* offset */
@@ -185,3 +185,3 @@
-/* Exeption event register - EXPEVT */
+/* Exception event register - EXPEVT */
#define SH7750_EXPEVT_REGOFS 0x000024
@@ -190,3 +190,3 @@
-#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */
+#define SH7750_EXPEVT_EX 0x00000fff /* Exception code */
#define SH7750_EXPEVT_EX_S 0
@@ -197,3 +197,3 @@
#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
-#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */
+#define SH7750_INTEVT_EX 0x00000fff /* Exception code */
#define SH7750_INTEVT_EX_S 0
@@ -1276,11 +1276,11 @@
*/
-#define SH7750_BARA 0x200000 /* Break address regiser A */
-#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */
-#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */
-#define SH7750_BARB 0x20000c /* Break address regiser B */
-#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */
-#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */
-#define SH7750_BASRB 0x000018 /* Break ASID regiser B */
-#define SH7750_BDRB 0x200018 /* Break data regiser B */
-#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */
+#define SH7750_BARA 0x200000 /* Break address register A */
+#define SH7750_BAMRA 0x200004 /* Break address mask register A */
+#define SH7750_BBRA 0x200008 /* Break bus cycle register A */
+#define SH7750_BARB 0x20000c /* Break address register B */
+#define SH7750_BAMRB 0x200010 /* Break address mask register B */
+#define SH7750_BBRB 0x200014 /* Break bus cycle register B */
+#define SH7750_BASRB 0x000018 /* Break ASID register B */
+#define SH7750_BDRB 0x200018 /* Break data register B */
+#define SH7750_BDMRB 0x20001c /* Break data mask register B */
#define SH7750_BRCR 0x200020 /* Break control register */
@@ -1112,3 +1112,3 @@ void smbios_get_tables(MachineState *ms,
/*
- * The offset determines if we need to keep additional space betweeen
+ * The offset determines if we need to keep additional space between
* table 17 and table 19 header handle numbers so that they do
@@ -165,3 +165,3 @@
FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
- /* QEMU doesnt care about any of these last three */
+ /* QEMU doesn't care about any of these last three */
FIELD(GQSPI_CNFG, BR, 3, 3)
@@ -471,3 +471,3 @@ static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
- /* immedate transfer */
+ /* immediate transfer */
if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
@@ -770,3 +770,3 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
- /* endianess just doesn't matter when zero pumping */
+ /* endianness just doesn't matter when zero pumping */
tx_data_bytes(&s->tx_fifo, 0, 4, false);
@@ -839,3 +839,3 @@ static void ospi_do_ind_read(XlnxVersalOspi *s)
!fifo8_is_full(&s->rx_sram)) {
- /* Read reqested number of bytes, max bytes limited to size of sram */
+ /* Read requested number of bytes, max bytes limited to size of sram */
next_b = ind_op_next_byte(op);
@@ -238,3 +238,3 @@ static void watchdog_hit(void *opaque)
if (t->wd_hits == 0) {
- /* real hw gives a single tick before reseting but we are
+ /* real hw gives a single tick before resetting but we are
a bit friendlier to compensate for our slower execution. */
@@ -297,3 +297,3 @@ static void pit_reset(DeviceState *dev)
/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
- * reenable it when legacy mode is left again. */
+ * re-enable it when legacy mode is left again. */
static void pit_irq_control(void *opaque, int n, int enable)
@@ -117,3 +117,3 @@ static int elapsed_time(RTMRState *tmr, int ch, int64_t delta)
} else {
- /* disble clock. so no update */
+ /* disable clock. so no update */
et = 0;
@@ -652,3 +652,3 @@ virtio_crypto_sym_op_helper(VirtIODevice *vdev,
op_info->len_to_cipher = len_to_cipher;
- /* Handle the initilization vector */
+ /* Handle the initialization vector */
if (op_info->iv_len > 0) {
@@ -1275,3 +1275,3 @@ static void virtio_crypto_instance_init(Object *obj)
* The default config_size is sizeof(struct virtio_crypto_config).
- * Can be overriden with virtio_crypto_set_config_size.
+ * Can be overridden with virtio_crypto_set_config_size.
*/
@@ -1121,3 +1121,3 @@ static int virtio_mem_mig_sanity_checks_post_load(void *opaque, int version_id)
/*
- * Note: Preparation for resizeable memory regions. The maximum size
+ * Note: Preparation for resizable memory regions. The maximum size
* of the memory region must not change during migration.
@@ -2098,3 +2098,3 @@ void virtio_queue_enable(VirtIODevice *vdev, uint32_t queue_index)
if (!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
- error_report("queue_enable is only suppported in devices of virtio "
+ error_report("queue_enable is only supported in devices of virtio "
"1.0 or later.");
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> --- hw/acpi/aml-build.c | 6 +++--- hw/acpi/hmat.c | 2 +- hw/acpi/nvdimm.c | 2 +- hw/block/hd-geometry.c | 4 ++-- hw/block/pflash_cfi01.c | 2 +- hw/char/cadence_uart.c | 2 +- hw/char/imx_serial.c | 2 +- hw/char/serial.c | 2 +- hw/core/generic-loader.c | 4 ++-- hw/core/loader.c | 4 ++-- hw/core/machine.c | 2 +- hw/core/qdev-properties-system.c | 2 +- hw/cpu/a15mpcore.c | 2 +- hw/cxl/cxl-events.c | 2 +- hw/cxl/cxl-mailbox-utils.c | 4 ++-- hw/dma/omap_dma.c | 4 ++-- hw/input/hid.c | 2 +- hw/input/tsc2005.c | 16 ++++++++-------- hw/intc/loongarch_extioi.c | 2 +- hw/intc/loongson_liointc.c | 2 +- hw/intc/omap_intc.c | 2 +- hw/intc/pnv_xive.c | 2 +- hw/intc/spapr_xive.c | 2 +- hw/intc/spapr_xive_kvm.c | 6 +++--- hw/intc/xive.c | 2 +- hw/intc/xive2.c | 6 +++--- hw/ipmi/ipmi_bmc_extern.c | 2 +- hw/mem/cxl_type3.c | 6 +++--- hw/misc/imx7_ccm.c | 2 +- hw/misc/mac_via.c | 2 +- hw/misc/stm32f2xx_syscfg.c | 4 ++-- hw/misc/trace-events | 2 +- hw/misc/zynq_slcr.c | 2 +- hw/nvme/ctrl.c | 6 +++--- hw/nvram/eeprom_at24c.c | 2 +- hw/nvram/fw_cfg.c | 2 +- hw/rtc/exynos4210_rtc.c | 2 +- hw/rx/rx62n.c | 2 +- hw/scsi/lsi53c895a.c | 2 +- hw/scsi/mfi.h | 2 +- hw/sd/sd.c | 2 +- hw/sd/sdhci.c | 2 +- hw/sensor/isl_pmbus_vr.c | 2 +- hw/sensor/max34451.c | 2 +- hw/sh4/sh7750_regs.h | 26 +++++++++++++------------- hw/smbios/smbios.c | 2 +- hw/ssi/xilinx_spips.c | 6 +++--- hw/ssi/xlnx-versal-ospi.c | 2 +- hw/timer/etraxfs_timer.c | 2 +- hw/timer/i8254.c | 2 +- hw/timer/renesas_tmr.c | 2 +- hw/virtio/virtio-crypto.c | 4 ++-- hw/virtio/virtio-mem.c | 2 +- hw/virtio/virtio.c | 2 +- 54 files changed, 92 insertions(+), 92 deletions(-)