@@ -241,3 +241,3 @@ VLIW packet semantics differ from serial semantics in that all input operands
are read, then the operations are performed, then all the results are written.
-For exmaple, this packet performs a swap of registers r0 and r1
+For example, this packet performs a swap of registers r0 and r1
{ r0 = r1; r1 = r0 }
@@ -417,3 +417,3 @@ static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \
* shifted out lots of bits from B, or if we had no shift / 1 shift sticky \
- * shoudl be 0 \
+ * should be 0 \
*/ \
@@ -442,3 +442,3 @@ Run-time errors can be divided between lexing and parsing errors, lexing errors
are hard to detect, since the ``var`` token will catch everything which is not
-catched by other tokens, but easy to fix, because most of the time a simple
+caught by other tokens, but easy to fix, because most of the time a simple
regex editing will be enough.
@@ -75,3 +75,3 @@ typedef struct HexTmp {
/**
- * Enum of the possible immediated, an immediate is a value which is known
+ * Enum of the possible immediate, an immediate is a value which is known
* at tinycode generation time, e.g. an integer value, not a TCGv
@@ -461,3 +461,3 @@ static bool try_find_variable(Context *c, YYLTYPE *locp,
-/* Calls `try_find_variable` and asserts succcess. */
+/* Calls `try_find_variable` and asserts success. */
static void find_variable(Context *c, YYLTYPE *locp,
@@ -551,3 +551,3 @@ HexValue gen_bin_cmp(Context *c,
default:
- fprintf(stderr, "Error in evalutating immediateness!");
+ fprintf(stderr, "Error in evaluating immediateness!");
abort();
@@ -1166,3 +1166,3 @@ void gen_rdeposit_op(Context *c,
* Otherwise if the width is not known, we fallback on reimplementing
- * desposit in TCG.
+ * deposit in TCG.
*/
@@ -294,12 +294,12 @@ Q6INSN(A4_combineii,"Rdd32=combine(#s8,#U6)",ATTRIBS(),"Set two small immediates
Q6INSN(A2_combine_hh,"Rd32=combine(Rt.H32,Rs.H32)",ATTRIBS(),
-"Combine two halfs into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(1,RsV);})
+"Combine two halves into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(1,RsV);})
Q6INSN(A2_combine_hl,"Rd32=combine(Rt.H32,Rs.L32)",ATTRIBS(),
-"Combine two halfs into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(0,RsV);})
+"Combine two halves into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(0,RsV);})
Q6INSN(A2_combine_lh,"Rd32=combine(Rt.L32,Rs.H32)",ATTRIBS(),
-"Combine two halfs into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(1,RsV);})
+"Combine two halves into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(1,RsV);})
Q6INSN(A2_combine_ll,"Rd32=combine(Rt.L32,Rs.L32)",ATTRIBS(),
-"Combine two halfs into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(0,RsV);})
+"Combine two halves into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(0,RsV);})
@@ -904,3 +904,3 @@ DEF_MACRO(
DEF_MACRO(
- fEA_GPI, /* Calculate EA with Global Poitner + Immediate */
+ fEA_GPI, /* Calculate EA with Global Pointer + Immediate */
do { EA=fREAD_GP()+IMM; fGP_DOCHKPAGECROSS(fREAD_GP(),EA); } while (0),
@@ -19,3 +19,3 @@
*
- * HOYA: MULTI MEDIA INSTRUCITONS
+ * HOYA: MULTI MEDIA INSTRUCTIONS
*
@@ -297,3 +297,3 @@ MMVEC_EACH_EA(vS32b_new,"Aligned Vector Store New",ATTRIBS(ATTR_VMEM,A_STORE,A_C
-// V65 store relase, zero byte store
+// V65 store release, zero byte store
MMVEC_EACH_EA(vS32b_srls,"Aligned Vector Scatter Release",ATTRIBS(ATTR_VMEM,A_STORE,A_CVI_SCATTER_RELEASE,A_CVI_NEW,A_RESTRICT_SLOT0ONLY),,"vmem",":scatter_release",fSTORERELEASE(EA,0))
@@ -2047,7 +2047,7 @@ VxV.uw[0] = RtV;)
-ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=vsplat(Rt32)", "Replicates scalar accross words in vector", VdV.uw[i] = RtV)
+ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=vsplat(Rt32)", "Replicates scalar across words in vector", VdV.uw[i] = RtV)
-ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=vsplat(Rt32)", "Replicates scalar accross halves in vector", VdV.uh[i] = RtV)
+ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=vsplat(Rt32)", "Replicates scalar across halves in vector", VdV.uh[i] = RtV)
-ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=vsplat(Rt32)", "Replicates scalar accross bytes in vector", VdV.ub[i] = RtV)
+ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=vsplat(Rt32)", "Replicates scalar across bytes in vector", VdV.ub[i] = RtV)
@@ -54,3 +54,3 @@ static void check_compare_exception(void)
- /* Check that FP compares are quiet (don't raise any execptions) */
+ /* Check that FP compares are quiet (don't raise any exceptions) */
asm (CLEAR_FPSTATUS
@@ -1,3 +1,3 @@
/*
- * Purpose: demonstrate the succesful operation of the register save mechanism,
+ * Purpose: demonstrate the successful operation of the register save mechanism,
* in which the caller saves the registers that will be clobbered, and restores
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> --- target/hexagon/README | 2 +- target/hexagon/fma_emu.c | 2 +- target/hexagon/idef-parser/README.rst | 2 +- target/hexagon/idef-parser/idef-parser.h | 2 +- target/hexagon/idef-parser/parser-helpers.c | 6 +++--- target/hexagon/imported/alu.idef | 8 ++++---- target/hexagon/imported/macros.def | 2 +- target/hexagon/imported/mmvec/ext.idef | 10 +++++----- tests/tcg/hexagon/fpstuff.c | 2 +- tests/tcg/hexagon/test_clobber.S | 2 +- 10 files changed, 19 insertions(+), 19 deletions(-)