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Fri, 14 Jul 2023 03:59:57 -0700 (PDT) X-Google-Smtp-Source: APBJJlEKqDmnaK25g9vSJmecSj+4wPjjaoRo5ReIXaKbKFABjCKPAaMTXJ9vGJmChfK/FxpETvF/vw== X-Received: by 2002:a05:600c:21c4:b0:3fb:b3f8:506b with SMTP id x4-20020a05600c21c400b003fbb3f8506bmr3719964wmj.24.1689332397061; Fri, 14 Jul 2023 03:59:57 -0700 (PDT) Received: from [192.168.10.118] ([2001:b07:6468:f312:63a7:c72e:ea0e:6045]) by smtp.gmail.com with ESMTPSA id m17-20020a7bce11000000b003fc07e17d4esm1184717wmc.2.2023.07.14.03.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 03:59:56 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Olaf Hering , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 1/5] hw/ide/piix: properly initialize the BMIBA register Date: Fri, 14 Jul 2023 12:59:49 +0200 Message-ID: <20230714105953.223485-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230714105953.223485-1-pbonzini@redhat.com> References: <20230714105953.223485-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Olaf Hering According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA-BUS MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is 32bit wide. To properly reset it to default values, all 32bit need to be cleared. Bit #0 "Resource Type Indicator (RTE)" needs to be enabled. The initial change wrote just the lower 8 bit, leaving parts of the "Bus Master Interface Base Address" address at bit 15:4 unchanged. Fixes: e6a71ae327 ("Add support for 82371FB (Step A1) and Improved support for 82371SB (Function 1)") Signed-off-by: Olaf Hering Reviewed-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230712074721.14728-1-olaf@aepfle.de> Signed-off-by: Paolo Bonzini --- hw/ide/piix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 151f206046e..4e5e12935f5 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -117,7 +117,7 @@ static void piix_ide_reset(DeviceState *dev) pci_set_word(pci_conf + PCI_COMMAND, 0x0000); pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); - pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ + pci_set_long(pci_conf + 0x20, 0x1); /* BMIBA: 20-23h */ } static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)