From patchwork Wed Jul 12 20:57:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1806991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=fU460uij; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R1VWV5vXJz20Ph for ; Thu, 13 Jul 2023 07:00:38 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qJgua-0000FI-Rn; Wed, 12 Jul 2023 16:58:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qJguZ-0000E4-AI for qemu-devel@nongnu.org; Wed, 12 Jul 2023 16:58:11 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qJguV-0005TU-F7 for qemu-devel@nongnu.org; Wed, 12 Jul 2023 16:58:11 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6b7206f106cso6075614a34.1 for ; Wed, 12 Jul 2023 13:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689195486; x=1691787486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4RiSgAfEWU0a1sAwwC0juXw9kQhptA+n3m54/TaSZbs=; b=fU460uijgNZaLaLOWDQFqKo99CtIS/FdRuzldPCobm977BVNzxIrdn98bljeep61b1 HF4uqqDI7yytKedhzNDKjLV7w8N7iHWfd2ONzw9tcwPrp6OoHD89TV7JiKp7wQ2S6ZjY +D/JKPK7EOpa5ZdNvZl33mh0Iruj5JeHWnfeZ1HRqhF+vKniu8oFFSWpYAULTSmcT8/1 egAdTHU361VwZkWYKDBZxG8Ef3xODQTHLHvZPFBlz5MwJxxsSusuEsr3Y5hNMdsSYpBC ffjFy3gJsXQi2FGRH9xs0eUz/U0+Pk/tC+63WS9ir4u8Ic+MG1gCaayMHchSWel7BG4t s9uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689195486; x=1691787486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4RiSgAfEWU0a1sAwwC0juXw9kQhptA+n3m54/TaSZbs=; b=ZlBgWRH+HCAQDKrB+Cab6cqRBO4VGuLTSIKHNKW441HlLluLxMviF3VSIklkg+lAAk GTT8qGFcIoyItDr8zVO5ld60aOrIhjXNJ0s2dxWsWn+MiUB9nArN796FzorVgWKIt6Js U50Wy5mIcppjz2/y3KD1apCq26KS6Ni+Y/s8xQlN2v4cxzREwfcx35Wdpg6JQmDz/xE8 it5KGea29F4t98ZDhYBirc/Th1F4zl7Hpyun1A72k9+E0t9E+2ZxnSNsM+vvQH6dlYLT 9LHoAeIvO8F8wRdlNpQ9SgYZKO87vLSdy1Z1ZNp2H8eUayiQyhVfWgq7FNfn5tB6GZ9f 0JWA== X-Gm-Message-State: ABy/qLbhVpaFZLdf41PJcmh9HB0fS5Z8HPWHEGrERc1F8ucYi1WFdSfc opHnRi7ikSrTQwifwJKjwK0er13rD0W9BwV++o4= X-Google-Smtp-Source: APBJJlGV4ZXVyx7X5652hXvBHOlve8oo7+ixM6IJDWHq64LuXa1qpgI8j/N9tjP/g4p41sC+Y4Lj+w== X-Received: by 2002:a05:6870:8a09:b0:1b0:449e:cff9 with SMTP id p9-20020a0568708a0900b001b0449ecff9mr21151422oaq.57.1689195485941; Wed, 12 Jul 2023 13:58:05 -0700 (PDT) Received: from grind.. (201-69-66-19.dial-up.telesp.net.br. [201.69.66.19]) by smtp.gmail.com with ESMTPSA id i2-20020a056870344200b001a9911765efsm2359904oah.40.2023.07.12.13.58.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 13:58:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.2 v2 1/7] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Date: Wed, 12 Jul 2023 17:57:42 -0300 Message-ID: <20230712205748.446931-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230712205748.446931-1-dbarboza@ventanamicro.com> References: <20230712205748.446931-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today. No functional changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..cdf9eeeb6b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1751,7 +1751,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -1767,11 +1766,6 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), @@ -1802,9 +1796,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), @@ -1848,6 +1840,20 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +static Property riscv_cpu_options[] = { + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + + DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), + + DEFINE_PROP_END_OF_LIST(), +}; #ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, @@ -1916,6 +1922,11 @@ static void riscv_cpu_add_user_properties(Object *obj) #endif qdev_property_add_static(dev, prop); } + + for (prop = riscv_cpu_options; prop && prop->name; prop++) { + qdev_property_add_static(dev, prop); + } + } static Property riscv_cpu_properties[] = {