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Tue, 11 Jul 2023 05:16:17 -0700 (PDT) Received: from m1x-phil.lan ([176.187.194.156]) by smtp.gmail.com with ESMTPSA id s15-20020adff80f000000b00313f9a0c521sm2120349wrp.107.2023.07.11.05.16.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 11 Jul 2023 05:16:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v3 15/16] target/riscv: Restrict TCG-specific prototype declarations Date: Tue, 11 Jul 2023 14:14:52 +0200 Message-Id: <20230711121453.59138-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230711121453.59138-1-philmd@linaro.org> References: <20230711121453.59138-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 3 +++ target/riscv/cpu.c | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6d78e59214..d2a9764317 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -479,7 +479,10 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); +#ifdef CONFIG_TCG void riscv_translate_init(void); +#endif + G_NORETURN void riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 91433f3041..c96819daf7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,7 +38,9 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" +#ifdef CONFIG_TCG #include "tcg/tcg.h" +#endif /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; @@ -782,6 +784,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } +#ifdef CONFIG_TCG static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -799,6 +802,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, } } } +#endif static bool riscv_cpu_has_work(CPUState *cs) { @@ -815,6 +819,7 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } +#ifdef CONFIG_TCG static void riscv_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -837,6 +842,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } env->bins = data[1]; } +#endif static void riscv_cpu_reset_hold(Object *obj) { @@ -1991,6 +1997,8 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { }; #endif +#ifdef CONFIG_TCG + #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps riscv_tcg_ops = { @@ -2009,6 +2017,7 @@ static const struct TCGCPUOps riscv_tcg_ops = { .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; +#endif /* CONFIG_TCG */ static bool riscv_cpu_is_dynamic(Object *cpu_obj) { @@ -2152,7 +2161,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; +#ifdef CONFIG_TCG cc->tcg_ops = &riscv_tcg_ops; +#endif /* CONFIG_TCG */ object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL);