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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id k3-20020a5d66c3000000b00314398e4dd4sm29988wrw.54.2023.07.10.10.51.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/11] hw/char/pl011: Split RX/TX path of pl011_reset_fifo() Date: Mon, 10 Jul 2023 19:50:56 +0200 Message-Id: <20230710175102.32429-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To be able to reset the RX or TX FIFO separately, split pl011_reset_fifo() in two. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 58edeb9ddb..1f07c7b021 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -132,14 +132,21 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s) return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; } -static inline void pl011_reset_fifo(PL011State *s) +static inline void pl011_reset_rx_fifo(PL011State *s) { s->read_count = 0; s->read_pos = 0; /* Reset FIFO flags */ - s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF); - s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE; + s->flags &= ~PL011_FLAG_RXFF; + s->flags |= PL011_FLAG_RXFE; +} + +static inline void pl011_reset_tx_fifo(PL011State *s) +{ + /* Reset FIFO flags */ + s->flags &= ~PL011_FLAG_TXFF; + s->flags |= PL011_FLAG_TXFE; } static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -289,7 +296,8 @@ static void pl011_write(void *opaque, hwaddr offset, case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & LCR_FEN) { - pl011_reset_fifo(s); + pl011_reset_rx_fifo(s); + pl011_reset_tx_fifo(s); } if ((s->lcr ^ value) & LCR_BRK) { int break_enable = value & LCR_BRK; @@ -506,7 +514,8 @@ static void pl011_reset(DeviceState *dev) s->ifl = 0x12; s->cr = 0x300; s->flags = 0; - pl011_reset_fifo(s); + pl011_reset_rx_fifo(s); + pl011_reset_tx_fifo(s); } static void pl011_class_init(ObjectClass *oc, void *data)