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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id u13-20020a7bcb0d000000b003fbc9b9699dsm433256wmj.45.2023.07.10.10.51.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/11] hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions Date: Mon, 10 Jul 2023 19:50:54 +0200 Message-Id: <20230710175102.32429-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org PL011_INT_TX duplicates INT_TX, and PL011_INT_RX INT_RX. Follow other register fields definitions from this file, keep the shorter form. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c3203e5b41..96675f52cc 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -48,9 +48,6 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) return dev; } -#define PL011_INT_TX 0x20 -#define PL011_INT_RX 0x10 - /* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 @@ -157,7 +154,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, s->flags |= PL011_FLAG_RXFE; } if (s->read_count == s->read_trigger - 1) - s->int_level &= ~ PL011_INT_RX; + s->int_level &= ~ INT_RX; trace_pl011_read_fifo(s->read_count); s->rsr = c >> 8; pl011_update(s); @@ -262,7 +259,7 @@ static void pl011_write(void *opaque, hwaddr offset, /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); - s->int_level |= PL011_INT_TX; + s->int_level |= INT_TX; pl011_update(s); break; case 1: /* UARTRSR/UARTECR */ @@ -350,7 +347,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { - s->int_level |= PL011_INT_RX; + s->int_level |= INT_RX; pl011_update(s); } }