Message ID | 20230706132512.3534397-15-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
Series | [PULL,01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance | expand |
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6eaf8e32cfa..6012e4ef549 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -122,10 +122,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) vq = ctz32(tmp) + 1; max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - vq_mask = MAKE_64BIT_MASK(0, max_vq); + vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0; vq_map = vq_supported & ~vq_init & vq_mask; - if (max_vq == 0 || vq_map == 0) { + if (vq_map == 0) { error_setg(errp, "cannot disable sve%d", vq * 128); error_append_hint(errp, "Disabling sve%d results in all " "vector lengths being disabled.\n",