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Tue, 04 Jul 2023 07:50:40 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id s7-20020adfeb07000000b0030ae901bc54sm28426750wrn.62.2023.07.04.07.50.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:50:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 05/19] hw/timer/arm_timer: CamelCase rename arm_timer_state -> ArmTimer Date: Tue, 4 Jul 2023 16:49:58 +0200 Message-Id: <20230704145012.49870-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Following docs/devel/style.rst guidelines, rename arm_timer_state as ArmTimer. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index c741e89cb4..8a2939483f 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -36,11 +36,11 @@ typedef struct { int freq; int int_level; qemu_irq irq; -} arm_timer_state; +} ArmTimer; /* Check all active timers, and schedule the next timer interrupt. */ -static void arm_timer_update(arm_timer_state *s) +static void arm_timer_update(ArmTimer *s) { /* Update interrupts. */ if (s->int_level && (s->control & TIMER_CTRL_IE)) { @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s = opaque; + ArmTimer *s = opaque; switch (offset >> 2) { case 0: /* TimerLoad */ @@ -79,7 +79,7 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) * Reset the timer limit after settings have changed. * May only be called from inside a ptimer transaction block. */ -static void arm_timer_recalibrate(arm_timer_state *s, int reload) +static void arm_timer_recalibrate(ArmTimer *s, int reload) { uint32_t limit; @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s = opaque; + ArmTimer *s = opaque; int freq; switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, static void arm_timer_tick(void *opaque) { - arm_timer_state *s = opaque; + ArmTimer *s = opaque; s->int_level = 1; arm_timer_update(s); } @@ -164,19 +164,19 @@ static const VMStateDescription vmstate_arm_timer = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32(control, arm_timer_state), - VMSTATE_UINT32(limit, arm_timer_state), - VMSTATE_INT32(int_level, arm_timer_state), - VMSTATE_PTIMER(timer, arm_timer_state), + VMSTATE_UINT32(control, ArmTimer), + VMSTATE_UINT32(limit, ArmTimer), + VMSTATE_INT32(int_level, ArmTimer), + VMSTATE_PTIMER(timer, ArmTimer), VMSTATE_END_OF_LIST() } }; -static arm_timer_state *arm_timer_init(uint32_t freq) +static ArmTimer *arm_timer_init(uint32_t freq) { - arm_timer_state *s; + ArmTimer *s; - s = g_new0(arm_timer_state, 1); + s = g_new0(ArmTimer, 1); s->freq = freq; s->control = TIMER_CTRL_IE; @@ -198,7 +198,7 @@ struct SP804State { SysBusDevice parent_obj; MemoryRegion iomem; - arm_timer_state *timer[2]; + ArmTimer *timer[2]; uint32_t freq0, freq1; int level[2]; qemu_irq irq; @@ -333,7 +333,7 @@ struct IntegratorPIT { SysBusDevice parent_obj; MemoryRegion iomem; - arm_timer_state *timer[3]; + ArmTimer *timer[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset,