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Tue, 04 Jul 2023 07:50:25 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id d5-20020adff845000000b003141b9ddab3sm13596392wrq.114.2023.07.04.07.50.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:50:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 02/19] hw/timer/arm_timer: Remove pointless cast from void * Date: Tue, 4 Jul 2023 16:49:55 +0200 Message-Id: <20230704145012.49870-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index e410b37a23..30a34a9a92 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; switch (offset >> 2) { case 0: /* TimerLoad */ @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; int freq; switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, static void arm_timer_tick(void *opaque) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; s->int_level = 1; arm_timer_update(s); } @@ -214,7 +214,7 @@ static const uint8_t sp804_ids[] = { /* Merge the IRQs from the two component devices. */ static void sp804_set_irq(void *opaque, int irq, int level) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; s->level[irq] = level; qemu_set_irq(s->irq, s->level[0] || s->level[1]); @@ -223,7 +223,7 @@ static void sp804_set_irq(void *opaque, int irq, int level) static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; if (offset < 0x20) { return arm_timer_read(s->timer[0], offset); @@ -255,7 +255,7 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); @@ -324,7 +324,7 @@ struct icp_pit_state { static uint64_t icp_pit_read(void *opaque, hwaddr offset, unsigned size) { - icp_pit_state *s = (icp_pit_state *)opaque; + icp_pit_state *s = opaque; int n; /* ??? Don't know the PrimeCell ID for this device. */ @@ -340,7 +340,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - icp_pit_state *s = (icp_pit_state *)opaque; + icp_pit_state *s = opaque; int n; n = offset >> 8;