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Tue, 04 Jul 2023 07:51:53 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id t1-20020adfe101000000b0030fb828511csm28523957wrz.100.2023.07.04.07.51.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 19/19] hw/timer/arm_timer: Map ARM_TIMER MMIO regions into SP804Timer Date: Tue, 4 Jul 2023 16:50:12 +0200 Message-Id: <20230704145012.49870-20-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=philmd@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instead of manually forwarding MMIO accesses to each ARM_TIMER, let have the generic memory code dispatch that for us. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 7b455aff4d..f8d65732dc 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -262,15 +262,6 @@ static const uint8_t sp804_ids[] = { static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804Timer *s = opaque; - - if (offset < 0x20) { - return arm_timer_read(&s->timer[0], offset, size); - } - if (offset < 0x40) { - return arm_timer_read(&s->timer[1], offset - 0x20, size); - } - /* TimerPeriphID */ if (offset >= 0xfe0 && offset <= 0xffc) { return sp804_ids[(offset - 0xfe0) >> 2]; @@ -294,18 +285,6 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804Timer *s = opaque; - - if (offset < 0x20) { - arm_timer_write(&s->timer[0], offset, value, size); - return; - } - - if (offset < 0x40) { - arm_timer_write(&s->timer[1], offset - 0x20, value, size); - return; - } - /* Technically we could be writing to the Test Registers, but not likely */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", __func__, (int)offset); @@ -374,6 +353,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) return; } sysbus_connect_irq(tmr, 0, qdev_get_gpio_in(DEVICE(&s->irq_orgate), i)); + memory_region_add_subregion_overlap(&s->iomem, 0x20 * i, + sysbus_mmio_get_region(tmr, 0), 1); } }