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Tue, 04 Jul 2023 07:51:06 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id j8-20020adfff88000000b0031412b685d2sm14988442wrr.32.2023.07.04.07.51.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 10/19] hw/timer/arm_timer: Rename arm_timer_init() -> arm_timer_new() Date: Tue, 4 Jul 2023 16:50:03 +0200 Message-Id: <20230704145012.49870-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org QDev models often use foo_new() as the combination of foo_init() + foo_realize(). Here arm_timer_init() is a such combination, so rename it as arm_timer_new() to emphasis the returned device is already realized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index cbd82e8365..4ef34b0f60 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -179,7 +179,7 @@ static void arm_timer_reset_hold(ArmTimer *s) s->control = TIMER_CTRL_IE; } -static ArmTimer *arm_timer_init(uint32_t freq) +static ArmTimer *arm_timer_new(uint32_t freq) { ArmTimer *s; @@ -310,8 +310,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804Timer *s = SP804_TIMER(dev); - s->timer[0] = arm_timer_init(s->freq0); - s->timer[1] = arm_timer_init(s->freq1); + s->timer[0] = arm_timer_new(s->freq0); + s->timer[1] = arm_timer_new(s->freq1); s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } @@ -386,10 +386,10 @@ static void icp_pit_init(Object *obj) SysBusDevice *dev = SYS_BUS_DEVICE(obj); /* Timer 0 runs at the system clock speed (40MHz). */ - s->timer[0] = arm_timer_init(40000000); + s->timer[0] = arm_timer_new(40000000); /* The other two timers run at 1MHz. */ - s->timer[1] = arm_timer_init(1000000); - s->timer[2] = arm_timer_init(1000000); + s->timer[1] = arm_timer_new(1000000); + s->timer[2] = arm_timer_new(1000000); sysbus_init_irq(dev, &s->timer[0]->irq); sysbus_init_irq(dev, &s->timer[1]->irq);