| Message ID | 20230704144848.164287-1-fbarrat@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | pnv/xive: Allow mmio operations of any size on the ESB CI pages | expand |
On 7/4/23 16:48, Frederic Barrat wrote: > We currently only allow 64-bit operations on the ESB CI pages. There's > no real reason for that limitation, skiboot/linux didn't need > more. However the hardware supports any size, so this patch relaxes > that restriction. It impacts both the ESB pages for "normal" > interrupts as well as the ESB pages for escalation interrupts defined > for the ENDs. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > > This should wrap-up the cleanup about mmio size for the xive BARs. The > NVPG and NVC BAR accesses should also be relaxed but we don't really > implement them, any load/store currently fails. Something to address > when/if we implement them. > > hw/intc/xive.c | 8 ++++---- > hw/intc/xive2.c | 4 ++-- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index f60c878345..c014e961a4 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -1175,11 +1175,11 @@ static const MemoryRegionOps xive_source_esb_ops = { > .write = xive_source_esb_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > }; > @@ -2006,11 +2006,11 @@ static const MemoryRegionOps xive_end_source_ops = { > .write = xive_end_source_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > }; > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 4d9ff41956..c37ef25d44 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -954,11 +954,11 @@ static const MemoryRegionOps xive2_end_source_ops = { > .write = xive2_end_source_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > };
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/4/23 11:48, Frederic Barrat wrote: > We currently only allow 64-bit operations on the ESB CI pages. There's > no real reason for that limitation, skiboot/linux didn't need > more. However the hardware supports any size, so this patch relaxes > that restriction. It impacts both the ESB pages for "normal" > interrupts as well as the ESB pages for escalation interrupts defined > for the ENDs. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- > > This should wrap-up the cleanup about mmio size for the xive BARs. The > NVPG and NVC BAR accesses should also be relaxed but we don't really > implement them, any load/store currently fails. Something to address > when/if we implement them. > > hw/intc/xive.c | 8 ++++---- > hw/intc/xive2.c | 4 ++-- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index f60c878345..c014e961a4 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -1175,11 +1175,11 @@ static const MemoryRegionOps xive_source_esb_ops = { > .write = xive_source_esb_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > }; > @@ -2006,11 +2006,11 @@ static const MemoryRegionOps xive_end_source_ops = { > .write = xive_end_source_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > }; > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 4d9ff41956..c37ef25d44 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -954,11 +954,11 @@ static const MemoryRegionOps xive2_end_source_ops = { > .write = xive2_end_source_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > };
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f60c878345..c014e961a4 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1175,11 +1175,11 @@ static const MemoryRegionOps xive_source_esb_ops = { .write = xive_source_esb_write, .endianness = DEVICE_BIG_ENDIAN, .valid = { - .min_access_size = 8, + .min_access_size = 1, .max_access_size = 8, }, .impl = { - .min_access_size = 8, + .min_access_size = 1, .max_access_size = 8, }, }; @@ -2006,11 +2006,11 @@ static const MemoryRegionOps xive_end_source_ops = { .write = xive_end_source_write, .endianness = DEVICE_BIG_ENDIAN, .valid = { - .min_access_size = 8, + .min_access_size = 1, .max_access_size = 8, }, .impl = { - .min_access_size = 8, + .min_access_size = 1, .max_access_size = 8, }, }; diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 4d9ff41956..c37ef25d44 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -954,11 +954,11 @@ static const MemoryRegionOps xive2_end_source_ops = { .write = xive2_end_source_write, .endianness = DEVICE_BIG_ENDIAN, .valid = { - .min_access_size = 8, + .min_access_size = 1, .max_access_size = 8, }, .impl = { - .min_access_size = 8, + .min_access_size = 1, .max_access_size = 8, }, };
We currently only allow 64-bit operations on the ESB CI pages. There's no real reason for that limitation, skiboot/linux didn't need more. However the hardware supports any size, so this patch relaxes that restriction. It impacts both the ESB pages for "normal" interrupts as well as the ESB pages for escalation interrupts defined for the ENDs. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- This should wrap-up the cleanup about mmio size for the xive BARs. The NVPG and NVC BAR accesses should also be relaxed but we don't really implement them, any load/store currently fails. Something to address when/if we implement them. hw/intc/xive.c | 8 ++++---- hw/intc/xive2.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-)