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([157.82.204.253]) by smtp.gmail.com with ESMTPSA id jd4-20020a170903260400b001b1920cffdasm5592452plb.204.2023.07.01.00.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jul 2023 00:02:00 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Ani Sinha , "Michael S . Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen , Akihiko Odaki Subject: [PATCH 3/4] igb: Fix ARI next function numbers Date: Sat, 1 Jul 2023 16:01:21 +0900 Message-ID: <20230701070133.24877-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230701070133.24877-1-akihiko.odaki@daynix.com> References: <20230701070133.24877-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::329; envelope-from=akihiko.odaki@daynix.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The next function numbers are expected to form a linked list ending with 0. Fixes: 3a977deebe ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- hw/net/igb_core.h | 3 +++ hw/net/igb.c | 4 +--- hw/net/igbvf.c | 5 ++++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/net/igb_core.h b/hw/net/igb_core.h index 9cbbfd516b..e1dab76995 100644 --- a/hw/net/igb_core.h +++ b/hw/net/igb_core.h @@ -49,6 +49,9 @@ #define IGB_NUM_QUEUES (16) #define IGB_NUM_VM_POOLS (8) +#define IGB_VF_OFFSET (0x80) +#define IGB_VF_STRIDE (2) + typedef struct IGBCore IGBCore; enum { PHY_R = BIT(0), diff --git a/hw/net/igb.c b/hw/net/igb.c index 1c989d7677..543ca0114a 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -81,8 +81,6 @@ struct IGBState { }; #define IGB_CAP_SRIOV_OFFSET (0x160) -#define IGB_VF_OFFSET (0x80) -#define IGB_VF_STRIDE (2) #define E1000E_MMIO_IDX 0 #define E1000E_FLASH_IDX 1 @@ -431,7 +429,7 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error **errp) hw_error("Failed to initialize AER capability"); } - pcie_ari_init(pci_dev, 0x150, 1); + pcie_ari_init(pci_dev, 0x150, IGB_VF_OFFSET); pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF, IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS, diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index 284ea61184..bf2f237ab5 100644 --- a/hw/net/igbvf.c +++ b/hw/net/igbvf.c @@ -240,6 +240,9 @@ static const MemoryRegionOps mmio_ops = { static void igbvf_pci_realize(PCIDevice *dev, Error **errp) { IgbVfState *s = IGBVF(dev); + uint16_t nextvfn = pcie_sriov_vf_number(dev) + 1; + uint16_t nextfn = nextvfn < IGB_MAX_VF_FUNCTIONS ? + IGB_VF_OFFSET + nextvfn * IGB_VF_STRIDE : 0; int ret; int i; @@ -270,7 +273,7 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp) hw_error("Failed to initialize AER capability"); } - pcie_ari_init(dev, 0x150, 1); + pcie_ari_init(dev, 0x150, nextfn); } static void igbvf_pci_uninit(PCIDevice *dev)