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([157.82.204.253]) by smtp.gmail.com with ESMTPSA id jd4-20020a170903260400b001b1920cffdasm5592452plb.204.2023.07.01.00.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jul 2023 00:01:57 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Ani Sinha , "Michael S . Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen , Akihiko Odaki Subject: [PATCH 2/4] hw/nvme: Fix ARI next function numbers Date: Sat, 1 Jul 2023 16:01:20 +0900 Message-ID: <20230701070133.24877-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230701070133.24877-1-akihiko.odaki@daynix.com> References: <20230701070133.24877-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::131; envelope-from=akihiko.odaki@daynix.com; helo=mail-il1-x131.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The next function numbers are expected to form a linked list ending with 0. Fixes: 44c2c09488 ("hw/nvme: Add support for SR-IOV") Signed-off-by: Akihiko Odaki --- hw/nvme/ctrl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index fd917fcda1..12500dc80b 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8088,7 +8088,12 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) pcie_endpoint_cap_init(pci_dev, 0x80); pcie_cap_flr_init(pci_dev); if (n->params.sriov_max_vfs) { - pcie_ari_init(pci_dev, 0x100, 1); + uint16_t nextvfn = pci_is_vf(pci_dev) ? + pcie_sriov_vf_number(pci_dev) + 1 : 0; + uint16_t nextfn = nextvfn < n->params.sriov_max_vfs ? + NVME_VF_OFFSET + nextvfn * NVME_VF_STRIDE : 0; + + pcie_ari_init(pci_dev, 0x100, nextfn); } /* add one to max_ioqpairs to account for the admin queue pair */