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Tue, 27 Jun 2023 23:32:56 -0700 (PDT) Received: from m1x-phil.lan ([176.187.207.229]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0031134bcdacdsm12446215wry.42.2023.06.27.23.32.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Jun 2023 23:32:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PATCH v2 3/4] target/riscv: Restrict 'rv128' machine to TCG accelerator Date: Wed, 28 Jun 2023 08:32:33 +0200 Message-Id: <20230628063234.32544-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230628063234.32544-1-philmd@linaro.org> References: <20230628063234.32544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We only build for 32/64-bit hosts, so TCG is required for 128-bit targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d9a3684b3e..5762ff68b4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -476,6 +476,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } +#ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -494,7 +495,10 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } -#else +#endif + +#else /* !TARGET_RISCV64 */ + static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -576,7 +580,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_icsr = true; cpu->cfg.pmp = true; } -#endif +#endif /* !TARGET_RISCV64 */ #if defined(CONFIG_KVM) static void riscv_host_cpu_init(Object *obj) @@ -1951,8 +1955,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), +#ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), -#endif +#endif /* CONFIG_TCG */ +#endif /* TARGET_RISCV64 */ }; DEFINE_TYPES(riscv_cpu_type_infos)