From patchwork Tue Jun 27 16:31:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1800735 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=kft0i1YF; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qr9N074mtz242J for ; Wed, 28 Jun 2023 02:36:48 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qEBcm-000434-U1; Tue, 27 Jun 2023 12:33:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qEBcW-0003dF-5t for qemu-devel@nongnu.org; Tue, 27 Jun 2023 12:32:49 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qEBcR-0004sS-TF for qemu-devel@nongnu.org; Tue, 27 Jun 2023 12:32:47 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-1b06a46e1a9so442033fac.2 for ; Tue, 27 Jun 2023 09:32:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687883562; x=1690475562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nvD2DfqdT0yLrhg4B8fLoR2B1muCOTUleRsfoLErt80=; b=kft0i1YFwXW5pvaeUrwlP216kbaJiF7wyBjhRcoUgi4mVjN/9KuNk1CoT+leLZ5jcR 1Xc03OeU+zmHtiCbp6yknjm+cNIvVsh9+rVsoHCbujkf1fht4eWNN1CYh7haeMGAtcuZ uHOSue9I/9GSyKDkDLR1FK9gtYpgXJuRNwhwAcHUUito85GLtJZRgPFtXRy5aM9RIev8 rCu8qSV/AuGmxNl3JJ5Kfh0Z7oR+j0vLnZZ8ECeV7msZstvjheZTNzgJCGCcqbTzHEff WuIlImS5gTzrbMhwUc5t0UGvcMNse6kJ9AQirzoTikB93hRFp4m7IdDKgi9EI4MlmCpA kLQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687883562; x=1690475562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nvD2DfqdT0yLrhg4B8fLoR2B1muCOTUleRsfoLErt80=; b=TQ0QS8GIim7pNQgAe1OiBExMG8qVbZTGdfeydTZ4pT0IRIVKuoVv9H45CuKhSaNmfj 78JApRY4SdsxSOeirm3kWbdw5G4WJvb8XKdWI+/VSTdtErtlUBq5czjVwxjZzvG+dnRs +YHF847uOFI6FCi1TAHmSqt83yqL+KdxeDO68XLA88MWTp2tLvIcXMq9tr7ZEEe4TA91 LPOGDrO+AF0A4hMpMiS+041oEAmbvboEYWfY9cHfcRbIICxtt+kUVBK8F63y+ExEvhG+ ejH4E+bFUoe81csZpAHWRqH8Z1yUU6LJIYep6bEYurd2qndC6trb4DS2ZB+KpOMNSXfi jOBQ== X-Gm-Message-State: AC+VfDyQg7wV3Dso+EByfsLYPuXo+hFTLv16iHWAR+qKcsUSAG6l4lM0 4w+EV9MqR7LTWHF94fWVtqXG4qtErbW6CXIWoCM= X-Google-Smtp-Source: ACHHUZ5k4eiTbG1Sb5BCeF0HcjGbmAU11Y1ZZWv6eDVBjz8DLpTIbmXqgsWv8Y+lN2MqdCv9WImobw== X-Received: by 2002:a05:6870:1729:b0:1b0:5218:ceff with SMTP id h41-20020a056870172900b001b05218ceffmr3558703oae.18.1687883562576; Tue, 27 Jun 2023 09:32:42 -0700 (PDT) Received: from grind.. (201-69-66-110.dial-up.telesp.net.br. [201.69.66.110]) by smtp.gmail.com with ESMTPSA id gu17-20020a056870ab1100b001a3093ec23fsm5254134oab.32.2023.06.27.09.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 09:32:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v5 10/19] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU Date: Tue, 27 Jun 2023 13:31:54 -0300 Message-ID: <20230627163203.49422-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627163203.49422-1-dbarboza@ventanamicro.com> References: <20230627163203.49422-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org At this moment we're retrieving env->misa_ext during kvm_arch_init_cpu(), leaving env->misa_ext_mask behind. We want to set env->misa_ext_mask, and we want to set it as early as possible. The reason is that we're going to use it in the validation process of the KVM MISA properties we're going to add next. Setting it during arch_init_cpu() is too late for user validation. Move the code to a new helper that is going to be called during init() time, via kvm_riscv_init_user_properties(), like we're already doing for the machine ID properties. Set both misa_ext and misa_ext_mask to the same value retrieved by the 'isa' config reg. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 602727cdfd..4d0808cb9a 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -396,6 +396,28 @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) } } +static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, + KVMScratchCPU *kvmcpu) +{ + CPURISCVState *env = &cpu->env; + struct kvm_one_reg reg; + int ret; + + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(isa)); + reg.addr = (uint64_t)&env->misa_ext_mask; + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + + if (ret) { + error_report("Unable to fetch ISA register from KVM, " + "error %d", ret); + kvm_riscv_destroy_scratch_vcpu(kvmcpu); + exit(EXIT_FAILURE); + } + + env->misa_ext = env->misa_ext_mask; +} + void kvm_riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu = RISCV_CPU(cpu_obj); @@ -406,6 +428,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) } kvm_riscv_init_machine_ids(cpu, &kvmcpu); + kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } @@ -525,21 +548,10 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) int kvm_arch_init_vcpu(CPUState *cs) { int ret = 0; - target_ulong isa; RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - uint64_t id; qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(isa)); - ret = kvm_get_one_reg(cs, id, &isa); - if (ret) { - return ret; - } - env->misa_ext = isa; - if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { ret = kvm_vcpu_set_machine_ids(cpu, cs); }