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[PULL,19/30] target/ppc: Better CTRL SPR implementation

Message ID 20230626055647.1147743-20-clg@kaod.org
State New
Headers show
Series [PULL,01/30] target/ppc: gdbstub init spr gdb_id for all CPUs | expand

Commit Message

Cédric Le Goater June 26, 2023, 5:56 a.m. UTC 
From: Nicholas Piggin <npiggin@gmail.com>

The CTRL register is able to write the bit in the RUN field, which gets
reflected into the TS field which is read-only and contains the state of
the RUN field for all threads in the core.

TCG does not implement SMT, so the correct implementation just requires
mirroring the RUN bit into the first bit of the TS field.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/translate.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
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Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b591f2e49600..1ade06361679 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -418,7 +418,14 @@  void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
 
 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
 {
-    spr_write_generic32(ctx, sprn, gprn);
+    /* This does not implement >1 thread */
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */
+    tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */
+    tcg_gen_or_tl(t1, t1, t0);
+    gen_store_spr(sprn, t1);
+    spr_store_dump_spr(sprn);
 
     /*
      * SPR_CTRL writes must force a new translation block,