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Fri, 23 Jun 2023 06:17:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5jLXQRmIcHmeLlaaXL6VfTZbo7dm/ZLSNOJzMMZ+Vb2JtUMQjXZgEt6gy9NppRBEvnzo3iEw== X-Received: by 2002:a17:907:3f18:b0:97d:ee91:df83 with SMTP id hq24-20020a1709073f1800b0097dee91df83mr22058692ejc.61.1687526244765; Fri, 23 Jun 2023 06:17:24 -0700 (PDT) Received: from [192.168.10.118] ([2001:b07:6468:f312:9af8:e5f5:7516:fa89]) by smtp.gmail.com with ESMTPSA id h11-20020a1709063b4b00b0098d80adcc23sm835924ejf.113.2023.06.23.06.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 06:17:24 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH v3 07/11] target/i386: Intel only supports SYSCALL/SYSRET in long mode Date: Fri, 23 Jun 2023 15:17:07 +0200 Message-ID: <20230623131711.96775-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230623131711.96775-1-pbonzini@redhat.com> References: <20230623131711.96775-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 4 ++++ target/i386/tcg/translate.c | 9 ++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 695e01582bf..978d24b5ec7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6238,6 +6238,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx |= 1 << 1; /* CmpLegacy bit */ } } + if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && + !(env->hflags & HF_LMA_MASK)) { + *edx &= ~CPUID_EXT2_SYSCALL; + } break; case 0x80000002: case 0x80000003: diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b2e2dccb84f..ed4016f554b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5692,7 +5692,10 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; #ifdef TARGET_X86_64 case 0x105: /* syscall */ - /* XXX: is it usable in real mode ? */ + /* For Intel SYSCALL is only valid in long mode */ + if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) { + goto illegal_op; + } gen_update_cc_op(s); gen_update_eip_cur(s); gen_helper_syscall(cpu_env, cur_insn_len_i32(s)); @@ -5702,6 +5705,10 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_eob_worker(s, false, true); break; case 0x107: /* sysret */ + /* For Intel SYSRET is only valid in long mode */ + if (!LMA(s) && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1) { + goto illegal_op; + } if (!PE(s)) { gen_exception_gpf(s); } else {