| Message ID | 20230622162527.1118350-2-fbarrat@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | pnv/xive2: Fix TIMA special ops detection | expand |
On 6/22/23 18:25, Frederic Barrat wrote: > The presenters for xive on P9 and P10 are mostly similar but the > behavior can be tuned through a few CQ registers. This patch adds a > "get_config" method, which will allow to access that config from the > presenter in a later patch. > For now, just define the config for the TIMA version. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > hw/intc/pnv_xive.c | 11 +++++++++++ > hw/intc/pnv_xive2.c | 12 ++++++++++++ > hw/intc/spapr_xive.c | 16 ++++++++++++++++ > hw/intc/xive.c | 7 +++++++ > include/hw/ppc/xive.h | 3 +++ > 5 files changed, 49 insertions(+) > > diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c > index 622f9d28b7..e536b3ec26 100644 > --- a/hw/intc/pnv_xive.c > +++ b/hw/intc/pnv_xive.c > @@ -479,6 +479,16 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, > return count; > } > > +static uint32_t pnv_xive_presenter_get_config(XivePresenter *xptr) > +{ > + uint32_t cfg = 0; > + > + /* TIMA GEN1 is all P9 knows */ > + cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; > + > + return cfg; > +} > + > static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) > { > return pnv_xive_block_id(PNV_XIVE(xrtr)); > @@ -1991,6 +2001,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) > > xnc->notify = pnv_xive_notify; > xpc->match_nvt = pnv_xive_match_nvt; > + xpc->get_config = pnv_xive_presenter_get_config; > }; > > static const TypeInfo pnv_xive_info = { > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index ec1edeb385..59534f6843 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -501,6 +501,17 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, > return count; > } > > +static uint32_t pnv_xive2_presenter_get_config(XivePresenter *xptr) > +{ > + PnvXive2 *xive = PNV_XIVE2(xptr); > + uint32_t cfg = 0; > + > + if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { > + cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; > + } > + return cfg; > +} > + > static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) > { > return pnv_xive2_block_id(PNV_XIVE2(xrtr)); > @@ -1987,6 +1998,7 @@ static void pnv_xive2_class_init(ObjectClass *klass, void *data) > xnc->notify = pnv_xive2_notify; > > xpc->match_nvt = pnv_xive2_match_nvt; > + xpc->get_config = pnv_xive2_presenter_get_config; > }; > > static const TypeInfo pnv_xive2_info = { > diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c > index dc641cc604..8bcab2846c 100644 > --- a/hw/intc/spapr_xive.c > +++ b/hw/intc/spapr_xive.c > @@ -475,6 +475,21 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, > return count; > } > > +static uint32_t spapr_xive_presenter_get_config(XivePresenter *xptr) > +{ > + uint32_t cfg = 0; > + > + /* > + * Let's claim GEN1 TIMA format. If running with KVM on P10, the > + * correct answer is deep in the hardware and not accessible to > + * us. But it shouldn't matter as it only affects the presenter > + * as seen by a guest OS. > + */ > + cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; On POWER10, real HW, a Gen2 TIMA layout is exposed to the OS, HV and guest. Gen2 and Gen1 being compatible, it is not a problem since Linux (this might not be true for other OS) doesn't use any of the new Gen2 bits. There is a larger bitfield for VP CAM, but that's HV world. Nevertheless, it might be good to expose a Gen2 OS layout when on POWER10 to be closer to reality, with a "property" may be. Who knows, one might implement the new Gen2 bits, but as of today, there is no difference in the OS ring of QEMU. No hurries. Thanks, C. > + > + return cfg; > +} > + > static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) > { > return SPAPR_XIVE_BLOCK_ID; > @@ -832,6 +847,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) > sicc->post_load = spapr_xive_post_load; > > xpc->match_nvt = spapr_xive_match_nvt; > + xpc->get_config = spapr_xive_presenter_get_config; > xpc->in_kernel = spapr_xive_in_kernel_xptr; > } > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 5204c14b87..34a868b185 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -461,6 +461,13 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, > } > } > > +static __attribute__((unused)) uint32_t xive_presenter_get_config(XivePresenter *xptr) > +{ > + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); > + > + return xpc->get_config(xptr); > +} > + > /* > * Define a mapping of "special" operations depending on the TIMA page > * offset and the size of the operation. > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h > index f7eea4ca81..3dfb06e002 100644 > --- a/include/hw/ppc/xive.h > +++ b/include/hw/ppc/xive.h > @@ -430,6 +430,8 @@ typedef struct XivePresenterClass XivePresenterClass; > DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER, > TYPE_XIVE_PRESENTER) > > +#define XIVE_PRESENTER_GEN1_TIMA_OS 0x1 > + > struct XivePresenterClass { > InterfaceClass parent; > int (*match_nvt)(XivePresenter *xptr, uint8_t format, > @@ -437,6 +439,7 @@ struct XivePresenterClass { > bool cam_ignore, uint8_t priority, > uint32_t logic_serv, XiveTCTXMatch *match); > bool (*in_kernel)(const XivePresenter *xptr); > + uint32_t (*get_config)(XivePresenter *xptr); > }; > > int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 622f9d28b7..e536b3ec26 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -479,6 +479,16 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +static uint32_t pnv_xive_presenter_get_config(XivePresenter *xptr) +{ + uint32_t cfg = 0; + + /* TIMA GEN1 is all P9 knows */ + cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; + + return cfg; +} + static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) { return pnv_xive_block_id(PNV_XIVE(xrtr)); @@ -1991,6 +2001,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) xnc->notify = pnv_xive_notify; xpc->match_nvt = pnv_xive_match_nvt; + xpc->get_config = pnv_xive_presenter_get_config; }; static const TypeInfo pnv_xive_info = { diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index ec1edeb385..59534f6843 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -501,6 +501,17 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +static uint32_t pnv_xive2_presenter_get_config(XivePresenter *xptr) +{ + PnvXive2 *xive = PNV_XIVE2(xptr); + uint32_t cfg = 0; + + if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { + cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; + } + return cfg; +} + static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) { return pnv_xive2_block_id(PNV_XIVE2(xrtr)); @@ -1987,6 +1998,7 @@ static void pnv_xive2_class_init(ObjectClass *klass, void *data) xnc->notify = pnv_xive2_notify; xpc->match_nvt = pnv_xive2_match_nvt; + xpc->get_config = pnv_xive2_presenter_get_config; }; static const TypeInfo pnv_xive2_info = { diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index dc641cc604..8bcab2846c 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -475,6 +475,21 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +static uint32_t spapr_xive_presenter_get_config(XivePresenter *xptr) +{ + uint32_t cfg = 0; + + /* + * Let's claim GEN1 TIMA format. If running with KVM on P10, the + * correct answer is deep in the hardware and not accessible to + * us. But it shouldn't matter as it only affects the presenter + * as seen by a guest OS. + */ + cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; + + return cfg; +} + static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) { return SPAPR_XIVE_BLOCK_ID; @@ -832,6 +847,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) sicc->post_load = spapr_xive_post_load; xpc->match_nvt = spapr_xive_match_nvt; + xpc->get_config = spapr_xive_presenter_get_config; xpc->in_kernel = spapr_xive_in_kernel_xptr; } diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5204c14b87..34a868b185 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -461,6 +461,13 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, } } +static __attribute__((unused)) uint32_t xive_presenter_get_config(XivePresenter *xptr) +{ + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); + + return xpc->get_config(xptr); +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index f7eea4ca81..3dfb06e002 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -430,6 +430,8 @@ typedef struct XivePresenterClass XivePresenterClass; DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER, TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_GEN1_TIMA_OS 0x1 + struct XivePresenterClass { InterfaceClass parent; int (*match_nvt)(XivePresenter *xptr, uint8_t format, @@ -437,6 +439,7 @@ struct XivePresenterClass { bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match); bool (*in_kernel)(const XivePresenter *xptr); + uint32_t (*get_config)(XivePresenter *xptr); }; int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
The presenters for xive on P9 and P10 are mostly similar but the behavior can be tuned through a few CQ registers. This patch adds a "get_config" method, which will allow to access that config from the presenter in a later patch. For now, just define the config for the TIMA version. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/intc/pnv_xive.c | 11 +++++++++++ hw/intc/pnv_xive2.c | 12 ++++++++++++ hw/intc/spapr_xive.c | 16 ++++++++++++++++ hw/intc/xive.c | 7 +++++++ include/hw/ppc/xive.h | 3 +++ 5 files changed, 49 insertions(+)