From patchwork Thu Jun 22 13:56:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1798414 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=LFifWDec; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qn25D2sX3z20Xt for ; Thu, 22 Jun 2023 23:58:08 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCKow-0007pa-Qi; Thu, 22 Jun 2023 09:57:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCKoo-0007dk-2l for qemu-devel@nongnu.org; Thu, 22 Jun 2023 09:57:51 -0400 Received: from mail-oo1-xc35.google.com ([2607:f8b0:4864:20::c35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCKol-0001dw-Lc for qemu-devel@nongnu.org; Thu, 22 Jun 2023 09:57:49 -0400 Received: by mail-oo1-xc35.google.com with SMTP id 006d021491bc7-5607b8c33ddso2875585eaf.0 for ; Thu, 22 Jun 2023 06:57:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687442266; x=1690034266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R8VqpGFPSGeVpgOJnRllgdcIk6EK894TdQ7CcFzt6AI=; b=LFifWDecJSt8oRcIWh60DoFvqQY6FlNrFhiWC1utih/Dr682zWuzebxSb499NIOCFi FM1hKlST2fAvnpwfigGpFMMJ9PG6WXjsPnpAUi85Gfvd6NcHqyh1f9vD2AnAqvPJMka+ ssKN9JKvOrhK9yhY//phWMdNDI/2mj81cSmUzy35uUFSksAEMFUNJvBQ6JYHmcFunavX 01QPGCHQ1EFYAODqqJ9vygRRWvQ12FetFCRrwqIQRGLCG+Z7VAbW1xf9TL3/T8CdHjF8 G9M8MWtCRvXHu9goEccIuFcDSbvo/BZ33HohgV7KQR1iw/f0ilD5lF5Z7PJDXg3E3JWS DWww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687442266; x=1690034266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R8VqpGFPSGeVpgOJnRllgdcIk6EK894TdQ7CcFzt6AI=; b=LnhQkfTdyQ2IEGGvceDmuD7VqTrmYWE5uP4pNzpYt7Y4r567z41QfG34MoPDRGS7fa 7sryB6S8n+SznQaiOf240t0pasdFBYuh+zNLRs20vIshY6FQk28je1C70gIxemhc/ynH NoltzkiySCJTv6htZysa4nyPrGKOvH7nojC9YFFf8ER96s0EztzrKqV+FiNeL+Y2yQGL Gf/32F6vQl5sVL8dto9/20+ivsQuVyPoYykRAXo1wIrQy2XfDMzJaVId/vD24dvMOnr7 dKqBiaQ5JRHA2cwN58tsCZ57p5jdp86bZnURkp1muAEyXpVPo/GYbP/A927jNtXFiX+t 1/pw== X-Gm-Message-State: AC+VfDyE5R2t8FJ2wBFOGamte6dswV/8FtLaRWFyjKet+jcGzpjk5orh adIQ1USM48/fR1O4uVO06Xxrn0pSshwINdKqrPE= X-Google-Smtp-Source: ACHHUZ44opfpw2iLogWIaT86QZJCUsehL3mtMdCSafdXfol4WoiK7bUsyOdV5oNjYCNhaT6mtQV8SA== X-Received: by 2002:a4a:bc01:0:b0:558:b482:c3b3 with SMTP id i1-20020a4abc01000000b00558b482c3b3mr9972666oop.1.1687442265811; Thu, 22 Jun 2023 06:57:45 -0700 (PDT) Received: from grind.. (201-69-66-110.dial-up.telesp.net.br. [201.69.66.110]) by smtp.gmail.com with ESMTPSA id w6-20020a4aa446000000b00562f06fb5easm156677ool.11.2023.06.22.06.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 06:57:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 12/19] target/riscv: add KVM specific MISA properties Date: Thu, 22 Jun 2023 10:56:53 -0300 Message-ID: <20230622135700.105383-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230622135700.105383-1-dbarboza@ventanamicro.com> References: <20230622135700.105383-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Using all TCG user properties in KVM is tricky. First because KVM supports only a small subset of what TCG provides, so most of the cpu->cfg flags do nothing for KVM. Second, and more important, we don't have a way of telling if any given value is an user input or not. For TCG this has a small impact since we just validating everything and error out if needed. But for KVM it would be good to know if a given value was set by the user or if it's a value already provided by KVM. Otherwise we don't know how to handle failed kvm_set_one_regs() when writing the configurations back. These characteristics make it overly complicated to use the same user facing flags for both KVM and TCG. A simpler approach is to create KVM specific properties that have specialized logic, forking KVM and TCG use cases for those cases only. Fully separating KVM/TCG properties is unneeded at this point - in fact we want the user experience to be as equal as possible, regardless of the acceleration chosen. We'll start this fork with the MISA properties, adding the MISA bits that the KVM driver currently supports. A new KVMCPUConfig type is introduced. It'll hold general information about an extension. For MISA extensions we're going to use the newly created misa_ext_infos[] to populate their name and description. 'offset' holds the MISA bit (RVA, RVC, ...). We're calling it 'offset' instead of 'misa_bit' because this same KVMCPUConfig struct will be used to multi-letter extensions later on. This new type also holds a 'user_set' flag. This flag will be set when the user set an option that's different than what is already configured in the host, requiring KVM intervention to write the regs back during kvm_arch_init_vcpu(). Similar mechanics will be implemented for multi-letter extensions as well. There is no need to duplicate more code than necessary, so we're going to use the existing kvm_riscv_init_user_properties() to add the KVM specific properties. Any code that is adding a TCG user prop is then changed slightly to verify first if there's a KVM prop with the same name already added. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 10 ++++++ target/riscv/kvm.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0e5d8b05a2..5a50cb1d0b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1610,6 +1610,11 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; + /* Check if KVM didn't create the property already */ + if (object_property_find(cpu_obj, misa_cfg->name)) { + continue; + } + object_property_add(cpu_obj, misa_cfg->name, "bool", cpu_get_misa_ext_cfg, cpu_set_misa_ext_cfg, @@ -1733,6 +1738,11 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_misa_properties(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { + /* Check if KVM didn't create the property already */ + if (object_property_find(obj, prop->name)) { + continue; + } + qdev_property_add_static(dev, prop); } diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 4d0808cb9a..fb5c5d4bfc 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -22,8 +22,10 @@ #include #include "qemu/timer.h" +#include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "qapi/visitor.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" @@ -105,6 +107,81 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, } \ } while (0) +typedef struct KVMCPUConfig { + const char *name; + const char *description; + target_ulong offset; + int kvm_reg_id; + bool user_set; +} KVMCPUConfig; + +#define KVM_MISA_CFG(_bit, _reg_id) \ + {.offset = _bit, .kvm_reg_id = _reg_id} + +/* KVM ISA extensions */ +static KVMCPUConfig kvm_misa_ext_cfgs[] = { + KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), + KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), + KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), + KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), + KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), + KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), + KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), +}; + +static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + KVMCPUConfig *misa_ext_cfg = opaque; + target_ulong misa_bit = misa_ext_cfg->offset; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + bool value, host_bit; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + host_bit = env->misa_ext_mask & misa_bit; + + if (value == host_bit) { + return; + } + + if (!value) { + misa_ext_cfg->user_set = true; + return; + } + + /* + * Forbid users to enable extensions that aren't + * available in the hart. + */ + error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " + "enabled in the host", misa_ext_cfg->name); +} + +static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { + KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; + int bit = misa_cfg->offset; + + misa_cfg->name = misa_ext_info_arr[bit].name; + misa_cfg->description = misa_ext_info_arr[bit].description; + + object_property_add(cpu_obj, misa_cfg->name, "bool", + NULL, + kvm_cpu_set_misa_ext_cfg, + NULL, misa_cfg); + object_property_set_description(cpu_obj, misa_cfg->name, + misa_cfg->description); + } +} + static int kvm_riscv_get_regs_core(CPUState *cs) { int ret = 0; @@ -427,6 +504,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) return; } + kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);