Message ID | 20230622093357.255649-3-npiggin@gmail.com |
---|---|
State | New |
Headers | show |
Series | target/ppc: TCG SMT support for spapr machine | expand |
On 6/22/23 11:33, Nicholas Piggin wrote: > A relatively simple case to begin with, CTRL is a SMT shared register > where reads and writes need to synchronise against state changes by > other threads in the core. > > Atomic serialisation operations are used to achieve this. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/helper.h | 2 ++ > target/ppc/misc_helper.c | 25 +++++++++++++++++++++++++ > target/ppc/translate.c | 18 +++++++++++++++++- > 3 files changed, 44 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 38efbc351c..fda40b8a60 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -704,6 +704,8 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl) > > DEF_HELPER_2(load_dump_spr, void, env, i32) > DEF_HELPER_2(store_dump_spr, void, env, i32) > +DEF_HELPER_3(spr_write_CTRL, void, env, i32, tl) > + > DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32) > DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32) > DEF_HELPER_FLAGS_1(load_tbl, TCG_CALL_NO_RWG, tl, env) > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c > index 40ddc5c08c..a058eb24cd 100644 > --- a/target/ppc/misc_helper.c > +++ b/target/ppc/misc_helper.c > @@ -43,6 +43,31 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) > env->spr[sprn]); > } > > +void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn, > + target_ulong val) > +{ > + CPUState *cs = env_cpu(env); > + CPUState *ccs; > + uint32_t run = val & 1; > + uint32_t ts, ts_mask; > + > + assert(sprn == SPR_CTRL); > + > + env->spr[sprn] &= ~1U; > + env->spr[sprn] |= run; > + > + ts_mask = ~(1U << (8 + env->spr[SPR_TIR])); > + ts = run << (8 + env->spr[SPR_TIR]); > + > + THREAD_SIBLING_FOREACH(cs, ccs) { > + CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; > + > + cenv->spr[sprn] &= ts_mask; > + cenv->spr[sprn] |= ts; > + } > +} > + > + > #ifdef TARGET_PPC64 > static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, > const char *caller, uint32_t cause, > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 5d585393c5..41a8b800bd 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -438,7 +438,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) > #endif > } > > -void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) > +static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) > { > /* This does not implement >1 thread */ > TCGv t0 = tcg_temp_new(); > @@ -447,6 +447,22 @@ void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) > tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ > tcg_gen_or_tl(t1, t1, t0); > gen_store_spr(sprn, t1); > +} > + > +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) > +{ > + if (!(ctx->flags & POWERPC_FLAG_SMT)) { > + spr_write_CTRL_ST(ctx, sprn, gprn); > + goto out; > + } > + > + if (!gen_serialize(ctx)) { > + return; > + } > + > + gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), > + cpu_gpr[gprn]); > +out: > spr_store_dump_spr(sprn); > > /*
diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 38efbc351c..fda40b8a60 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -704,6 +704,8 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl) DEF_HELPER_2(load_dump_spr, void, env, i32) DEF_HELPER_2(store_dump_spr, void, env, i32) +DEF_HELPER_3(spr_write_CTRL, void, env, i32, tl) + DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32) DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32) DEF_HELPER_FLAGS_1(load_tbl, TCG_CALL_NO_RWG, tl, env) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 40ddc5c08c..a058eb24cd 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -43,6 +43,31 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) env->spr[sprn]); } +void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn, + target_ulong val) +{ + CPUState *cs = env_cpu(env); + CPUState *ccs; + uint32_t run = val & 1; + uint32_t ts, ts_mask; + + assert(sprn == SPR_CTRL); + + env->spr[sprn] &= ~1U; + env->spr[sprn] |= run; + + ts_mask = ~(1U << (8 + env->spr[SPR_TIR])); + ts = run << (8 + env->spr[SPR_TIR]); + + THREAD_SIBLING_FOREACH(cs, ccs) { + CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; + + cenv->spr[sprn] &= ts_mask; + cenv->spr[sprn] |= ts; + } +} + + #ifdef TARGET_PPC64 static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, const char *caller, uint32_t cause, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5d585393c5..41a8b800bd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -438,7 +438,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) #endif } -void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) { /* This does not implement >1 thread */ TCGv t0 = tcg_temp_new(); @@ -447,6 +447,22 @@ void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ tcg_gen_or_tl(t1, t1, t0); gen_store_spr(sprn, t1); +} + +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +{ + if (!(ctx->flags & POWERPC_FLAG_SMT)) { + spr_write_CTRL_ST(ctx, sprn, gprn); + goto out; + } + + if (!gen_serialize(ctx)) { + return; + } + + gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), + cpu_gpr[gprn]); +out: spr_store_dump_spr(sprn); /*
A relatively simple case to begin with, CTRL is a SMT shared register where reads and writes need to synchronise against state changes by other threads in the core. Atomic serialisation operations are used to achieve this. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/helper.h | 2 ++ target/ppc/misc_helper.c | 25 +++++++++++++++++++++++++ target/ppc/translate.c | 18 +++++++++++++++++- 3 files changed, 44 insertions(+), 1 deletion(-)