| Message ID | 20230622093357.255649-2-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/ppc: TCG SMT support for spapr machine | expand |
On 6/22/23 11:33, Nicholas Piggin wrote: > TGC SMT emulation needs to know whether it is running with SMT siblings, > to be able to iterate over siblings in a core, and to serialise > threads to access per-core shared SPRs. Add infrastructure to do these > things. > > For now the sibling iteration and serialisation are implemented in a > simple but inefficient way. SMT shared state and sibling access is not > too common, and SMT configurations are mainly useful to test system > code, so performance is not to critical. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/cpu.h | 9 +++++++++ > target/ppc/cpu_init.c | 5 +++++ > target/ppc/translate.c | 20 ++++++++++++++++++++ > 3 files changed, 34 insertions(+) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index bfa1777289..0087ce66e2 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -672,6 +672,8 @@ enum { > POWERPC_FLAG_TM = 0x00100000, > /* Has SCV (ISA 3.00) */ > POWERPC_FLAG_SCV = 0x00200000, > + /* Has >1 thread per core */ > + POWERPC_FLAG_SMT = 0x00400000, > }; > > /* > @@ -1270,6 +1272,13 @@ struct CPUArchState { > uint64_t pmu_base_time; > }; > > +#define _CORE_ID(cs) \ > + (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1)) > + > +#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ > + CPU_FOREACH(cs_sibling) \ > + if (_CORE_ID(cs) == _CORE_ID(cs_sibling)) > + > #define SET_FIT_PERIOD(a_, b_, c_, d_) \ > do { \ > env->fit_period[0] = (a_); \ > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index dccc064053..aeff71d063 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6755,6 +6755,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > PowerPCCPU *cpu = POWERPC_CPU(dev); > + CPUPPCState *env = &cpu->env; > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > Error *local_err = NULL; > > @@ -6786,6 +6787,10 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) > > pcc->parent_realize(dev, errp); > > + if (env_cpu(env)->nr_threads > 1) { > + env->flags |= POWERPC_FLAG_SMT; > + } > + > return; > > unrealize: > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index b62b624682..5d585393c5 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -236,6 +236,26 @@ struct opc_handler_t { > void (*handler)(DisasContext *ctx); > }; > > +static inline bool gen_serialize(DisasContext *ctx) > +{ > + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { > + /* Restart with exclusive lock. */ > + gen_helper_exit_atomic(cpu_env); > + ctx->base.is_jmp = DISAS_NORETURN; > + return false; > + } > + return true; > +} > + > +static inline bool gen_serialize_core(DisasContext *ctx) > +{ > + if (ctx->flags & POWERPC_FLAG_SMT) { > + return gen_serialize(ctx); > + } > + > + return true; > +} > + > /* SPR load/store helpers */ > static inline void gen_load_spr(TCGv t, int reg) > {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bfa1777289..0087ce66e2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -672,6 +672,8 @@ enum { POWERPC_FLAG_TM = 0x00100000, /* Has SCV (ISA 3.00) */ POWERPC_FLAG_SCV = 0x00200000, + /* Has >1 thread per core */ + POWERPC_FLAG_SMT = 0x00400000, }; /* @@ -1270,6 +1272,13 @@ struct CPUArchState { uint64_t pmu_base_time; }; +#define _CORE_ID(cs) \ + (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1)) + +#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ + CPU_FOREACH(cs_sibling) \ + if (_CORE_ID(cs) == _CORE_ID(cs_sibling)) + #define SET_FIT_PERIOD(a_, b_, c_, d_) \ do { \ env->fit_period[0] = (a_); \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index dccc064053..aeff71d063 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6755,6 +6755,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); PowerPCCPU *cpu = POWERPC_CPU(dev); + CPUPPCState *env = &cpu->env; PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); Error *local_err = NULL; @@ -6786,6 +6787,10 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) pcc->parent_realize(dev, errp); + if (env_cpu(env)->nr_threads > 1) { + env->flags |= POWERPC_FLAG_SMT; + } + return; unrealize: diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b62b624682..5d585393c5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -236,6 +236,26 @@ struct opc_handler_t { void (*handler)(DisasContext *ctx); }; +static inline bool gen_serialize(DisasContext *ctx) +{ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; + return false; + } + return true; +} + +static inline bool gen_serialize_core(DisasContext *ctx) +{ + if (ctx->flags & POWERPC_FLAG_SMT) { + return gen_serialize(ctx); + } + + return true; +} + /* SPR load/store helpers */ static inline void gen_load_spr(TCGv t, int reg) {
TGC SMT emulation needs to know whether it is running with SMT siblings, to be able to iterate over siblings in a core, and to serialise threads to access per-core shared SPRs. Add infrastructure to do these things. For now the sibling iteration and serialisation are implemented in a simple but inefficient way. SMT shared state and sibling access is not too common, and SMT configurations are mainly useful to test system code, so performance is not to critical. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/cpu.h | 9 +++++++++ target/ppc/cpu_init.c | 5 +++++ target/ppc/translate.c | 20 ++++++++++++++++++++ 3 files changed, 34 insertions(+)