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[PULL,13/20] target/tricore: Fix RR_JLI clobbering reg A[11]

Message ID 20230621161422.1652151-14-kbastian@mail.uni-paderborn.de
State New
Headers show
Series [PULL,01/20] target/tricore: Introduce ISA 1.6.2 feature | expand

Commit Message

Bastian Koppelmann June 21, 2023, 4:14 p.m. UTC 
if A[r1] == A[11], then we would overwrite the destination address of
the jump with the return address.

Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-2-kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d1b319e374..cca52c75b2 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6064,8 +6064,8 @@  static void decode_rr_idirect(DisasContext *ctx)
         tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
         break;
     case OPC2_32_RR_JLI:
-        tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
         tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
+        tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
         break;
     case OPC2_32_RR_CALLI:
         gen_helper_1arg(call, ctx->pc_succ_insn);