| Message ID | 20230616143803.73926-1-kinsey.moore@oarcorp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] hw/arm/xlnx: Connect secondary CGEM IRQs | expand |
On [2023 Jun 16] Fri 09:38:03, Kinsey Moore wrote: > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > platforms have two priority queues with separate interrupt sources for > each. If the interrupt source for the second priority queue is not > connected, they work in polling mode only. This change connects the > second interrupt source for platforms where it is available. This patch > has been tested using the lwIP stack with a Xilinx-supplied driver from > their embeddedsw repository. > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> > --- > hw/arm/xlnx-versal.c | 12 +++++++++++- > hw/arm/xlnx-zynqmp.c | 11 ++++++++++- > include/hw/arm/xlnx-versal.h | 1 + > include/hw/arm/xlnx-zynqmp.h | 1 + > 4 files changed, 23 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 60bf5fe657..cb79b855fd 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -252,9 +252,13 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) > NICInfo *nd = &nd_table[i]; > DeviceState *dev; > MemoryRegion *mr; > + OrIRQState *or_irq; > > object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], > TYPE_CADENCE_GEM); > + or_irq = &s->lpd.iou.gem_irq_orgate[i]; > + object_initialize_child(OBJECT(s), "gem-irq-orgate[*]", > + or_irq, TYPE_OR_IRQ); > dev = DEVICE(&s->lpd.iou.gem[i]); > /* FIXME use qdev NIC properties instead of nd_table[] */ > if (nd->used) { > @@ -264,6 +268,11 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) > object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); > object_property_set_int(OBJECT(dev), "num-priority-queues", 2, > &error_abort); > + object_property_set_int(OBJECT(or_irq), > + "num-lines", 2, &error_fatal); > + qdev_realize(DEVICE(or_irq), NULL, &error_fatal); > + qdev_connect_gpio_out(DEVICE(or_irq), 0, pic[irqs[i]]); > + > object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), > &error_abort); > sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); > @@ -271,7 +280,8 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) > mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); > memory_region_add_subregion(&s->mr_ps, addrs[i], mr); > > - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(or_irq), 0)); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(or_irq), 1)); > g_free(name); > } > } > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 5905a33015..f7158e4fd3 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -392,6 +392,8 @@ static void xlnx_zynqmp_init(Object *obj) > > for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { > object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); > + object_initialize_child(obj, "gem-irq-orgate[*]", > + &s->gem_irq_orgate[i], TYPE_OR_IRQ); > } > > for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { > @@ -629,12 +631,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > &error_abort); > object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, > &error_abort); > + object_property_set_int(OBJECT(&s->gem_irq_orgate[i]), > + "num-lines", 2, &error_fatal); > + qdev_realize(DEVICE(&s->gem_irq_orgate[i]), NULL, &error_fatal); > + qdev_connect_gpio_out(DEVICE(&s->gem_irq_orgate[i]), 0, gic_spi[gem_intr[i]]); > + > if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { > return; > } > sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, > - gic_spi[gem_intr[i]]); > + qdev_get_gpio_in(DEVICE(&s->gem_irq_orgate[i]), 0)); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, > + qdev_get_gpio_in(DEVICE(&s->gem_irq_orgate[i]), 1)); > } > > for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { > diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h > index 39ee31185c..d34c763329 100644 > --- a/include/hw/arm/xlnx-versal.h > +++ b/include/hw/arm/xlnx-versal.h > @@ -74,6 +74,7 @@ struct Versal { > struct { > PL011State uart[XLNX_VERSAL_NR_UARTS]; > CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; > + OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS]; > XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; > VersalUsb2 usb; > CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 687c75e3b0..7e5abce467 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -117,6 +117,7 @@ struct XlnxZynqMPState { > MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; > > CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; > + OrIRQState gem_irq_orgate[XLNX_ZYNQMP_NUM_GEMS]; > CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; > XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; > SysbusAHCIState sata; > -- > 2.30.2 > >
On 16/6/23 16:38, Kinsey Moore wrote: > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > platforms have two priority queues with separate interrupt sources for > each. If the interrupt source for the second priority queue is not > connected, they work in polling mode only. This change connects the > second interrupt source for platforms where it is available. This patch > has been tested using the lwIP stack with a Xilinx-supplied driver from > their embeddedsw repository. > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> > --- > hw/arm/xlnx-versal.c | 12 +++++++++++- > hw/arm/xlnx-zynqmp.c | 11 ++++++++++- > include/hw/arm/xlnx-versal.h | 1 + > include/hw/arm/xlnx-zynqmp.h | 1 + > 4 files changed, 23 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+PMM (I think this one might have fallen throught the cracks) Best regards, Francisco Iglesias On [2023 Jun 18] Sun 00:50:47, Philippe Mathieu-Daudé wrote: > On 16/6/23 16:38, Kinsey Moore wrote: > > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > > platforms have two priority queues with separate interrupt sources for > > each. If the interrupt source for the second priority queue is not > > connected, they work in polling mode only. This change connects the > > second interrupt source for platforms where it is available. This patch > > has been tested using the lwIP stack with a Xilinx-supplied driver from > > their embeddedsw repository. > > > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> > > --- > > hw/arm/xlnx-versal.c | 12 +++++++++++- > > hw/arm/xlnx-zynqmp.c | 11 ++++++++++- > > include/hw/arm/xlnx-versal.h | 1 + > > include/hw/arm/xlnx-zynqmp.h | 1 + > > 4 files changed, 23 insertions(+), 2 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > >
Hey, I just wanted to check on the status of this patch since it's been sitting for a bit now and I noticed it hasn't gone into any branches. Is this waiting on something from me? Thanks, Kinsey -----Original Message----- From: Francisco Iglesias <frasse.iglesias@gmail.com> Sent: Monday, July 10, 2023 09:10 To: peter.maydell@linaro.org Cc: Kinsey Moore <kinsey.moore@oarcorp.com>; qemu-devel@nongnu.org; philmd@linaro.org Subject: Re: [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs +PMM (I think this one might have fallen throught the cracks) Best regards, Francisco Iglesias On [2023 Jun 18] Sun 00:50:47, Philippe Mathieu-Daudé wrote: > On 16/6/23 16:38, Kinsey Moore wrote: > > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > > platforms have two priority queues with separate interrupt sources for > > each. If the interrupt source for the second priority queue is not > > connected, they work in polling mode only. This change connects the > > second interrupt source for platforms where it is available. This patch > > has been tested using the lwIP stack with a Xilinx-supplied driver from > > their embeddedsw repository. > > > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> > > --- > > hw/arm/xlnx-versal.c | 12 +++++++++++- > > hw/arm/xlnx-zynqmp.c | 11 ++++++++++- > > include/hw/arm/xlnx-versal.h | 1 + > > include/hw/arm/xlnx-zynqmp.h | 1 + > > 4 files changed, 23 insertions(+), 2 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > >
On Wed, 25 Sept 2024 at 20:34, Kinsey Moore <kinsey.moore@oarcorp.com> wrote: > > Hey, > I just wanted to check on the status of this patch since it's been sitting for a bit now and I noticed it hasn't gone into any branches. Is this waiting on something from me? No, I'm afraid I just hadn't noticed it to pick it up. I've applied it to target-arm.next now; sorry about the delay. (Generally if nothing seems to have happened to a patch you can 'ping' it on the mailing list after a couple of weeks to get somebody's attention on it.) thanks -- PMM > Thanks, > Kinsey > > -----Original Message----- > From: Francisco Iglesias <frasse.iglesias@gmail.com> > Sent: Monday, July 10, 2023 09:10 > To: peter.maydell@linaro.org > Cc: Kinsey Moore <kinsey.moore@oarcorp.com>; qemu-devel@nongnu.org; philmd@linaro.org > Subject: Re: [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs > > > +PMM (I think this one might have fallen throught the cracks) > > Best regards, > Francisco Iglesias > > On [2023 Jun 18] Sun 00:50:47, Philippe Mathieu-Daudé wrote: > > On 16/6/23 16:38, Kinsey Moore wrote: > > > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > > > platforms have two priority queues with separate interrupt sources for > > > each. If the interrupt source for the second priority queue is not > > > connected, they work in polling mode only. This change connects the > > > second interrupt source for platforms where it is available. This patch > > > has been tested using the lwIP stack with a Xilinx-supplied driver from > > > their embeddedsw repository. > > > > > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> > > > --- > > > hw/arm/xlnx-versal.c | 12 +++++++++++- > > > hw/arm/xlnx-zynqmp.c | 11 ++++++++++- > > > include/hw/arm/xlnx-versal.h | 1 + > > > include/hw/arm/xlnx-zynqmp.h | 1 + > > > 4 files changed, 23 insertions(+), 2 deletions(-) > > > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > > > >
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 60bf5fe657..cb79b855fd 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -252,9 +252,13 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) NICInfo *nd = &nd_table[i]; DeviceState *dev; MemoryRegion *mr; + OrIRQState *or_irq; object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], TYPE_CADENCE_GEM); + or_irq = &s->lpd.iou.gem_irq_orgate[i]; + object_initialize_child(OBJECT(s), "gem-irq-orgate[*]", + or_irq, TYPE_OR_IRQ); dev = DEVICE(&s->lpd.iou.gem[i]); /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd->used) { @@ -264,6 +268,11 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); object_property_set_int(OBJECT(dev), "num-priority-queues", 2, &error_abort); + object_property_set_int(OBJECT(or_irq), + "num-lines", 2, &error_fatal); + qdev_realize(DEVICE(or_irq), NULL, &error_fatal); + qdev_connect_gpio_out(DEVICE(or_irq), 0, pic[irqs[i]]); + object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), &error_abort); sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); @@ -271,7 +280,8 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->mr_ps, addrs[i], mr); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(or_irq), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(or_irq), 1)); g_free(name); } } diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5905a33015..f7158e4fd3 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -392,6 +392,8 @@ static void xlnx_zynqmp_init(Object *obj) for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); + object_initialize_child(obj, "gem-irq-orgate[*]", + &s->gem_irq_orgate[i], TYPE_OR_IRQ); } for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { @@ -629,12 +631,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, &error_abort); + object_property_set_int(OBJECT(&s->gem_irq_orgate[i]), + "num-lines", 2, &error_fatal); + qdev_realize(DEVICE(&s->gem_irq_orgate[i]), NULL, &error_fatal); + qdev_connect_gpio_out(DEVICE(&s->gem_irq_orgate[i]), 0, gic_spi[gem_intr[i]]); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, - gic_spi[gem_intr[i]]); + qdev_get_gpio_in(DEVICE(&s->gem_irq_orgate[i]), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, + qdev_get_gpio_in(DEVICE(&s->gem_irq_orgate[i]), 1)); } for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 39ee31185c..d34c763329 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -74,6 +74,7 @@ struct Versal { struct { PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; + OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; VersalUsb2 usb; CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 687c75e3b0..7e5abce467 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -117,6 +117,7 @@ struct XlnxZynqMPState { MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; + OrIRQState gem_irq_orgate[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; SysbusAHCIState sata;
The Cadence GEM peripherals as configured for Zynq MPSoC and Versal platforms have two priority queues with separate interrupt sources for each. If the interrupt source for the second priority queue is not connected, they work in polling mode only. This change connects the second interrupt source for platforms where it is available. This patch has been tested using the lwIP stack with a Xilinx-supplied driver from their embeddedsw repository. Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> --- hw/arm/xlnx-versal.c | 12 +++++++++++- hw/arm/xlnx-zynqmp.c | 11 ++++++++++- include/hw/arm/xlnx-versal.h | 1 + include/hw/arm/xlnx-zynqmp.h | 1 + 4 files changed, 23 insertions(+), 2 deletions(-)