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bh=eZMV03luAtuQ4QX2gz4oqDQWTuWWgUuUqFQDNsSStCY=; b=cME5x9qz9zROhPkGSWFJZMCebd ygA2qUmZXlH1Jg4wRvCOsbimGRH2JI6rTYYNWm8XKVt60/CQZn8576h34KxXma/DUbkJDIoL9hf/H aIh/LXFX68hW1RwD9Iw/U+VN1SdWk4Yewh1gZqluvZVoU1T7W9/qm2zZVJlk7IF1ElvE=; X-Envelope-From: From: Bastian Koppelmann To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org Subject: [PATCH 1/4] target/tricore: Introduce priv tb flag Date: Wed, 14 Jun 2023 18:59:31 +0200 Message-Id: <20230614165934.1370440-2-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230614165934.1370440-1-kbastian@mail.uni-paderborn.de> References: <20230614165934.1370440-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.9.2830568, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2023.6.14.165116, AntiVirus-Engine: 6.0.0, AntiVirus-Data: 2023.6.14.600000 X-Sophos-SenderHistory: ip=79.202.219.6, fs=606881, da=174371054, mc=74, sc=0, hc=74, sp=0, fso=606881, re=0, sd=0, hd=0 X-IMT-Source: Intern X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de Received-SPF: pass client-ip=2001:638:502:c003::16; envelope-from=kbastian@mail.uni-paderborn.de; helo=doohan.uni-paderborn.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target/tricore/cpu.h | 17 ++++++++++++----- target/tricore/translate.c | 15 +++++++++------ 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 041fc0b6e5..257fcf3cee 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -263,10 +263,11 @@ void icr_set_ie(CPUTriCoreState *env, uint32_t val); #define MASK_DBGSR_PEVT 0x40 #define MASK_DBGSR_EVTSRC 0x1f00 -#define TRICORE_HFLAG_KUU 0x3 -#define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ -#define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ -#define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ +enum tricore_priv_levels { + TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */ + TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */ + TRICORE_PRIV_SM = 0x2, /* kernel mode flag */ +}; enum tricore_features { TRICORE_FEATURE_13, @@ -378,15 +379,21 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) #include "exec/cpu-all.h" +FIELD(TB_FLAGS, PRIV, 0, 2) + void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { + uint32_t new_flags = 0; *pc = env->PC; *cs_base = 0; - *flags = 0; + + new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags = new_flags; } #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6712d98f6e..a0644dd120 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -32,6 +32,7 @@ #include "tricore-opcodes.h" #include "exec/translator.h" #include "exec/log.h" +#include "hw/registerfields.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" @@ -73,7 +74,7 @@ typedef struct DisasContext { uint32_t opcode; /* Routine used to access memory */ int mem_idx; - uint32_t hflags, saved_hflags; + int priv; uint64_t features; uint32_t icr_ie_mask, icr_ie_offset; } DisasContext; @@ -374,7 +375,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) static inline void gen_mtcr(DisasContext *ctx, TCGv r1, int32_t offset) { - if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { + if (ctx->priv == TRICORE_PRIV_SM) { /* since we're caching PSW make this a special case */ if (offset == 0xfe04) { gen_helper_psw_write(cpu_env, r1); @@ -7911,7 +7912,7 @@ static void decode_sys_interrupts(DisasContext *ctx) ctx->base.is_jmp = DISAS_NORETURN; break; case OPC2_32_SYS_RFM: - if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { + if (ctx->priv == TRICORE_PRIV_SM) { tmp = tcg_temp_new(); l1 = gen_new_label(); @@ -7934,8 +7935,7 @@ static void decode_sys_interrupts(DisasContext *ctx) break; case OPC2_32_SYS_RESTORE: if (has_feature(ctx, TRICORE_FEATURE_16)) { - if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || - (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { + if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); } /* else raise privilege trap */ } else { @@ -8305,7 +8305,10 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUTriCoreState *env = cs->env_ptr; ctx->mem_idx = cpu_mmu_index(env, false); - ctx->hflags = (uint32_t)ctx->base.tb->flags; + + uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; + ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); + ctx->features = env->features; if (has_feature(ctx, TRICORE_FEATURE_161)) { ctx->icr_ie_mask = R_ICR_IE_161_MASK;