Message ID | 20230613205857.495165-12-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | target/riscv, KVM: fixes and enhancements | expand |
On Tue, Jun 13, 2023 at 05:58:50PM -0300, Daniel Henrique Barboza wrote: > Next patch will add KVM specific user properties for both MISA and > multi-letter extensions. For MISA extensions we want to make use of what > is already available in misa_ext_cfgs[] to avoid code repetition. > > The new misa_ext_infos[] array will hold name and description for each > MISA extension that misa_ext_cfgs[] is declaring. We'll then use this > new array in KVM code to avoid duplicating strings. > > There's nothing holding us back from doing the same with multi-letter > extensions. For now doing just with MISA extensions is enough. > > Suggested-by: Andrew Jones <ajones@ventanamicro.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 44 ++++++++++++++++++-------------------------- > target/riscv/cpu.h | 22 +++++++++++++++++++++- > 2 files changed, 39 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0b25d53bbe..edaf052f25 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1562,33 +1562,25 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > visit_type_bool(v, name, &value, errp); > } > > +#define MISA_CFG(_bit, _enabled) \ > + {.name = misa_ext_infos[_bit].name, \ Maybe just misa_ext_info[] for the name? 'infos' sounds odd to me. > + .description = misa_ext_infos[_bit].description, \ > + .misa_bit = _bit, .enabled = _enabled} > + > static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > - {.name = "a", .description = "Atomic instructions", > - .misa_bit = RVA, .enabled = true}, > - {.name = "c", .description = "Compressed instructions", > - .misa_bit = RVC, .enabled = true}, > - {.name = "d", .description = "Double-precision float point", > - .misa_bit = RVD, .enabled = true}, > - {.name = "f", .description = "Single-precision float point", > - .misa_bit = RVF, .enabled = true}, > - {.name = "i", .description = "Base integer instruction set", > - .misa_bit = RVI, .enabled = true}, > - {.name = "e", .description = "Base integer instruction set (embedded)", > - .misa_bit = RVE, .enabled = false}, > - {.name = "m", .description = "Integer multiplication and division", > - .misa_bit = RVM, .enabled = true}, > - {.name = "s", .description = "Supervisor-level instructions", > - .misa_bit = RVS, .enabled = true}, > - {.name = "u", .description = "User-level instructions", > - .misa_bit = RVU, .enabled = true}, > - {.name = "h", .description = "Hypervisor", > - .misa_bit = RVH, .enabled = true}, > - {.name = "x-j", .description = "Dynamic translated languages", > - .misa_bit = RVJ, .enabled = false}, > - {.name = "v", .description = "Vector operations", > - .misa_bit = RVV, .enabled = false}, > - {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", > - .misa_bit = RVG, .enabled = false}, > + MISA_CFG(RVA, true), > + MISA_CFG(RVC, true), > + MISA_CFG(RVD, true), > + MISA_CFG(RVF, true), > + MISA_CFG(RVI, true), > + MISA_CFG(RVE, false), > + MISA_CFG(RVM, true), > + MISA_CFG(RVS, true), > + MISA_CFG(RVU, true), > + MISA_CFG(RVH, true), > + MISA_CFG(RVJ, false), > + MISA_CFG(RVV, false), > + MISA_CFG(RVG, false), > }; > > static void riscv_cpu_add_misa_properties(Object *cpu_obj) > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e3e08d315f..6d2acea478 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -41,7 +41,7 @@ > > #define RV(x) ((target_ulong)1 << (x - 'A')) > > -/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ > +/* Consider updating misa_ext_infos[] when adding new MISA bits here */ Both arrays (_cfgs and _info) need consideration, right? > #define RVI RV('I') > #define RVE RV('E') /* E and I are mutually exclusive */ > #define RVM RV('M') > @@ -56,6 +56,26 @@ > #define RVJ RV('J') > #define RVG RV('G') > > +typedef struct misa_ext_info { > + const char *name; > + const char *description; > +} MISAExtInfo; > + > +static const MISAExtInfo misa_ext_infos[] = { > + [RVA] = {"a", "Atomic instructions"}, > + [RVC] = {"c", "Compressed instructions"}, > + [RVD] = {"d", "Double-precision float point"}, > + [RVF] = {"f", "Single-precision float point"}, > + [RVI] = {"i", "Base integer instruction set"}, > + [RVE] = {"e", "Base integer instruction set (embedded)"}, > + [RVM] = {"m", "Integer multiplication and division"}, > + [RVS] = {"s", "Supervisor-level instructions"}, > + [RVU] = {"u", "User-level instructions"}, > + [RVH] = {"h", "Hypervisor"}, > + [RVJ] = {"x-j", "Dynamic translated languages"}, > + [RVV] = {"v", "Vector operations"}, > + [RVG] = {"g", "General purpose (IMAFD_Zicsr_Zifencei)"}, > +}; I'd export this array from target/riscv/cpu.c, rather than having each source file that includes this header get its own copy. Thanks, drew
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0b25d53bbe..edaf052f25 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1562,33 +1562,25 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, visit_type_bool(v, name, &value, errp); } +#define MISA_CFG(_bit, _enabled) \ + {.name = misa_ext_infos[_bit].name, \ + .description = misa_ext_infos[_bit].description, \ + .misa_bit = _bit, .enabled = _enabled} + static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { - {.name = "a", .description = "Atomic instructions", - .misa_bit = RVA, .enabled = true}, - {.name = "c", .description = "Compressed instructions", - .misa_bit = RVC, .enabled = true}, - {.name = "d", .description = "Double-precision float point", - .misa_bit = RVD, .enabled = true}, - {.name = "f", .description = "Single-precision float point", - .misa_bit = RVF, .enabled = true}, - {.name = "i", .description = "Base integer instruction set", - .misa_bit = RVI, .enabled = true}, - {.name = "e", .description = "Base integer instruction set (embedded)", - .misa_bit = RVE, .enabled = false}, - {.name = "m", .description = "Integer multiplication and division", - .misa_bit = RVM, .enabled = true}, - {.name = "s", .description = "Supervisor-level instructions", - .misa_bit = RVS, .enabled = true}, - {.name = "u", .description = "User-level instructions", - .misa_bit = RVU, .enabled = true}, - {.name = "h", .description = "Hypervisor", - .misa_bit = RVH, .enabled = true}, - {.name = "x-j", .description = "Dynamic translated languages", - .misa_bit = RVJ, .enabled = false}, - {.name = "v", .description = "Vector operations", - .misa_bit = RVV, .enabled = false}, - {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", - .misa_bit = RVG, .enabled = false}, + MISA_CFG(RVA, true), + MISA_CFG(RVC, true), + MISA_CFG(RVD, true), + MISA_CFG(RVF, true), + MISA_CFG(RVI, true), + MISA_CFG(RVE, false), + MISA_CFG(RVM, true), + MISA_CFG(RVS, true), + MISA_CFG(RVU, true), + MISA_CFG(RVH, true), + MISA_CFG(RVJ, false), + MISA_CFG(RVV, false), + MISA_CFG(RVG, false), }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e3e08d315f..6d2acea478 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -41,7 +41,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) -/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ +/* Consider updating misa_ext_infos[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') @@ -56,6 +56,26 @@ #define RVJ RV('J') #define RVG RV('G') +typedef struct misa_ext_info { + const char *name; + const char *description; +} MISAExtInfo; + +static const MISAExtInfo misa_ext_infos[] = { + [RVA] = {"a", "Atomic instructions"}, + [RVC] = {"c", "Compressed instructions"}, + [RVD] = {"d", "Double-precision float point"}, + [RVF] = {"f", "Single-precision float point"}, + [RVI] = {"i", "Base integer instruction set"}, + [RVE] = {"e", "Base integer instruction set (embedded)"}, + [RVM] = {"m", "Integer multiplication and division"}, + [RVS] = {"s", "Supervisor-level instructions"}, + [RVU] = {"u", "User-level instructions"}, + [RVH] = {"h", "Hypervisor"}, + [RVJ] = {"x-j", "Dynamic translated languages"}, + [RVV] = {"v", "Vector operations"}, + [RVG] = {"g", "General purpose (IMAFD_Zicsr_Zifencei)"}, +}; /* Privileged specification version */ enum {
Next patch will add KVM specific user properties for both MISA and multi-letter extensions. For MISA extensions we want to make use of what is already available in misa_ext_cfgs[] to avoid code repetition. The new misa_ext_infos[] array will hold name and description for each MISA extension that misa_ext_cfgs[] is declaring. We'll then use this new array in KVM code to avoid duplicating strings. There's nothing holding us back from doing the same with multi-letter extensions. For now doing just with MISA extensions is enough. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 44 ++++++++++++++++++-------------------------- target/riscv/cpu.h | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 27 deletions(-)