| Message ID | 20230605025445.161932-4-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/4] target/ppc: Fix lqarx to set cpu_reserve | expand |
On 6/4/23 23:54, Nicholas Piggin wrote: > Rework store conditional to avoid a branch in the success case. > Change some of the variable names and layout while here so > gen_conditional_store more closely matches gen_stqcx_. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- Queued. Thanks, Daniel > v2: > - Reinstate lost DEF_MEMOP [Richard] > > I think the DEF_MEMOP is redundant here, but admit that's not something > that should be changed with this patch. I will look at cleaning those up > later. > > Thanks, > Nick > > target/ppc/translate.c | 63 ++++++++++++++++++++---------------------- > 1 file changed, 30 insertions(+), 33 deletions(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index acb99d8691..434caad258 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -3813,31 +3813,32 @@ static void gen_stdat(DisasContext *ctx) > > static void gen_conditional_store(DisasContext *ctx, MemOp memop) > { > - TCGLabel *l1 = gen_new_label(); > - TCGLabel *l2 = gen_new_label(); > - TCGv t0 = tcg_temp_new(); > - int reg = rS(ctx->opcode); > + TCGLabel *lfail; > + TCGv EA; > + TCGv cr0; > + TCGv t0; > + int rs = rS(ctx->opcode); > > + lfail = gen_new_label(); > + EA = tcg_temp_new(); > + cr0 = tcg_temp_new(); > + t0 = tcg_temp_new(); > + > + tcg_gen_mov_tl(cr0, cpu_so); > gen_set_access_type(ctx, ACCESS_RES); > - gen_addr_reg_index(ctx, t0); > - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); > - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), l1); > + gen_addr_reg_index(ctx, EA); > + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); > + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); > > - t0 = tcg_temp_new(); > tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, > - cpu_gpr[reg], ctx->mem_idx, > + cpu_gpr[rs], ctx->mem_idx, > DEF_MEMOP(memop) | MO_ALIGN); > tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); > tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); > - tcg_gen_or_tl(t0, t0, cpu_so); > - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); > - tcg_gen_br(l2); > + tcg_gen_or_tl(cr0, cr0, t0); > > - gen_set_label(l1); > - > - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); > - > - gen_set_label(l2); > + gen_set_label(lfail); > + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); > tcg_gen_movi_tl(cpu_reserve, -1); > } > > @@ -3891,25 +3892,26 @@ static void gen_lqarx(DisasContext *ctx) > /* stqcx. */ > static void gen_stqcx_(DisasContext *ctx) > { > - TCGLabel *lab_fail, *lab_over; > - int rs = rS(ctx->opcode); > + TCGLabel *lfail; > TCGv EA, t0, t1; > + TCGv cr0; > TCGv_i128 cmp, val; > + int rs = rS(ctx->opcode); > > if (unlikely(rs & 1)) { > gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); > return; > } > > - lab_fail = gen_new_label(); > - lab_over = gen_new_label(); > + lfail = gen_new_label(); > + EA = tcg_temp_new(); > + cr0 = tcg_temp_new(); > > + tcg_gen_mov_tl(cr0, cpu_so); > gen_set_access_type(ctx, ACCESS_RES); > - EA = tcg_temp_new(); > gen_addr_reg_index(ctx, EA); > - > - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); > - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lab_fail); > + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); > + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); > > cmp = tcg_temp_new_i128(); > val = tcg_temp_new_i128(); > @@ -3932,15 +3934,10 @@ static void gen_stqcx_(DisasContext *ctx) > > tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); > tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); > - tcg_gen_or_tl(t0, t0, cpu_so); > - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); > - > - tcg_gen_br(lab_over); > - gen_set_label(lab_fail); > - > - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); > + tcg_gen_or_tl(cr0, cr0, t0); > > - gen_set_label(lab_over); > + gen_set_label(lfail); > + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); > tcg_gen_movi_tl(cpu_reserve, -1); > } > #endif /* defined(TARGET_PPC64) */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index acb99d8691..434caad258 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3813,31 +3813,32 @@ static void gen_stdat(DisasContext *ctx) static void gen_conditional_store(DisasContext *ctx, MemOp memop) { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv t0 = tcg_temp_new(); - int reg = rS(ctx->opcode); + TCGLabel *lfail; + TCGv EA; + TCGv cr0; + TCGv t0; + int rs = rS(ctx->opcode); + lfail = gen_new_label(); + EA = tcg_temp_new(); + cr0 = tcg_temp_new(); + t0 = tcg_temp_new(); + + tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), l1); + gen_addr_reg_index(ctx, EA); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); - t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, - cpu_gpr[reg], ctx->mem_idx, + cpu_gpr[rs], ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(t0, t0, cpu_so); - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - tcg_gen_br(l2); + tcg_gen_or_tl(cr0, cr0, t0); - gen_set_label(l1); - - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(l2); + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } @@ -3891,25 +3892,26 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { - TCGLabel *lab_fail, *lab_over; - int rs = rS(ctx->opcode); + TCGLabel *lfail; TCGv EA, t0, t1; + TCGv cr0; TCGv_i128 cmp, val; + int rs = rS(ctx->opcode); if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } - lab_fail = gen_new_label(); - lab_over = gen_new_label(); + lfail = gen_new_label(); + EA = tcg_temp_new(); + cr0 = tcg_temp_new(); + tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); - EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lab_fail); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); cmp = tcg_temp_new_i128(); val = tcg_temp_new_i128(); @@ -3932,15 +3934,10 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(t0, t0, cpu_so); - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - - tcg_gen_br(lab_over); - gen_set_label(lab_fail); - - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_or_tl(cr0, cr0, t0); - gen_set_label(lab_over); + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */