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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id c10-20020a4a4f0a000000b005462a25c4f9sm9665764oob.9.2023.04.28.09.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 09:52:50 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [PATCH v3 3/4] target/riscv: check smstateen fcsr flag Date: Fri, 28 Apr 2023 22:22:10 +0530 Message-Id: <20230428165212.2800669-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230428165212.2800669-1-mchitale@ventanamicro.com> References: <20230428165212.2800669-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=mchitale@ventanamicro.com; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If misa.F and smstateen_fcsr_ok flag are clear then all the floating point instructions must generate an appropriate exception. Signed-off-by: Mayuresh Chitale --- target/riscv/insn_trans/trans_rvd.c.inc | 13 ++++++--- target/riscv/insn_trans/trans_rvf.c.inc | 24 ++++++++++++++--- target/riscv/insn_trans/trans_rvzfh.c.inc | 32 +++++++++++++++-------- 3 files changed, 50 insertions(+), 19 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 2c51e01c40..d9e0cf116f 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -18,10 +18,15 @@ * this program. If not, see . */ -#define REQUIRE_ZDINX_OR_D(ctx) do { \ - if (!ctx->cfg_ptr->ext_zdinx) { \ - REQUIRE_EXT(ctx, RVD); \ - } \ +#define REQUIRE_ZDINX_OR_D(ctx) do { \ + if (!has_ext(ctx, RVD)) { \ + if (!ctx->cfg_ptr->ext_zdinx) { \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ + } \ } while (0) #define REQUIRE_EVEN(ctx, reg) do { \ diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index b2de4fcf3f..e4d9834237 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -24,10 +24,26 @@ return false; \ } while (0) -#define REQUIRE_ZFINX_OR_F(ctx) do {\ - if (!ctx->cfg_ptr->ext_zfinx) { \ - REQUIRE_EXT(ctx, RVF); \ - } \ +static inline bool smstateen_fcsr_check(DisasContext *ctx) +{ +#ifndef CONFIG_USER_ONLY + if (!ctx->smstateen_fcsr_ok) { + ctx->virt_inst_excp = ctx->virt_enabled; + return false; + } +#endif + return true; +} + +#define REQUIRE_ZFINX_OR_F(ctx) do { \ + if (!has_ext(ctx, RVF)) { \ + if (!ctx->cfg_ptr->ext_zfinx) { \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ + } \ } while (0) #define REQUIRE_ZCF(ctx) do { \ diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 74dde37ff7..e228ae28a5 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -16,28 +16,38 @@ * this program. If not, see . */ -#define REQUIRE_ZFH(ctx) do { \ +#define REQUIRE_ZFH(ctx) do { \ if (!ctx->cfg_ptr->ext_zfh) { \ - return false; \ - } \ -} while (0) - -#define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ - if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ } while (0) +#define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ + if (!ctx->cfg_ptr->ext_zfh) { \ + if (!ctx->cfg_ptr->ext_zhinx) { \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ + } \ +} while (0) + #define REQUIRE_ZFHMIN(ctx) do { \ if (!ctx->cfg_ptr->ext_zfhmin) { \ return false; \ } \ } while (0) -#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \ - if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \ - return false; \ - } \ +#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \ + if (!ctx->cfg_ptr->ext_zfhmin) { \ + if (ctx->cfg_ptr->ext_zhinxmin) { \ + return false; \ + } \ + if (!smstateen_fcsr_check(ctx)) { \ + return false; \ + } \ + } \ } while (0) static bool trans_flh(DisasContext *ctx, arg_flh *a)