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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:46 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 10/13] hw/ide/piix: Reuse PCIIDEState::{cmd,data}_ops Date: Sat, 22 Apr 2023 17:07:25 +0200 Message-Id: <20230422150728.176512-11-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=shentey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Now that PCIIDEState::{cmd,data}_ops are initialized in the base class constructor there is an opportunity for PIIX to reuse these attributes. This resolves usage of ide_init_ioport() which would fall back internally to using the isabus global due to NULL being passed as ISADevice by PIIX. Signed-off-by: Bernhard Beschow --- hw/ide/piix.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index a3a15dc7db..406a67fa0f 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -104,34 +104,32 @@ static void piix_ide_reset(DeviceState *dev) pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ } -static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus *isa_bus, - Error **errp) +static void pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus *isa_bus) { static const struct { int iobase; int iobase2; int isairq; } port_info[] = { - {0x1f0, 0x3f6, 14}, - {0x170, 0x376, 15}, + {0x1f0, 0x3f4, 14}, + {0x170, 0x374, 15}, }; - int ret; + MemoryRegion *address_space_io = pci_address_space_io(PCI_DEVICE(d)); ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); - ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, - port_info[i].iobase2); - if (ret) { - error_setg_errno(errp, -ret, "Failed to realize %s port %u", - object_get_typename(OBJECT(d)), i); - return false; - } + memory_region_add_subregion(address_space_io, port_info[i].iobase, + &d->data_ops[i]); + /* + * PIIX forwards the last byte of cmd_ops to ISA. Model this using a low + * prio so competing memory regions take precedence. + */ + memory_region_add_subregion_overlap(address_space_io, port_info[i].iobase2, + &d->cmd_ops[i], -1); ide_bus_init_output_irq(&d->bus[i], isa_bus_get_irq(isa_bus, port_info[i].isairq)); bmdma_init(&d->bus[i], &d->bmdma[i], d); ide_bus_register_restart_cb(&d->bus[i]); - - return true; } static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) @@ -160,9 +158,7 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) } for (unsigned i = 0; i < 2; i++) { - if (!pci_piix_init_bus(d, i, isa_bus, errp)) { - return; - } + pci_piix_init_bus(d, i, isa_bus); } }