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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id u6-20020a4a5706000000b00524fe20aee5sm1794323ooa.34.2023.04.14.09.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:02:39 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [RFC PATCH v2 2/4] target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS Date: Fri, 14 Apr 2023 21:32:00 +0530 Message-Id: <20230414160202.1298242-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160202.1298242-1-mchitale@ventanamicro.com> References: <20230414160202.1298242-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/cpu_helper.c | 12 ++++++++++++ target/riscv/translate.c | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 433ea529b0..fd1731cc39 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,6 +105,18 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } + /* + * If misa.F is 0 then the MSTATUS_HS_FS field of the tb->flags + * can be used to pass the current state of the smstateen.FCSR bit + * which must be checked for in the floating point translation routines + */ + if (!riscv_has_ext(env, RVF)) { + if (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) { + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 1); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 0); + } + } if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0094922b6..e29bbb8b70 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -79,6 +79,7 @@ typedef struct DisasContext { int frm; RISCVMXL ol; bool virt_inst_excp; + bool smstateen_fcsr_ok; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; bool hlsx; @@ -1202,6 +1203,12 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; + if (has_ext(ctx, RVF)) { + ctx->smstateen_fcsr_ok = 1; + } else { + ctx->smstateen_fcsr_ok = FIELD_EX32(tb_flags, TB_FLAGS, + MSTATUS_HS_FS); + } } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)