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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id b22-20020aa78716000000b0063486255a87sm3783526pfo.142.2023.04.10.07.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 07:13:36 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags Date: Mon, 10 Apr 2023 19:43:14 +0530 Message-Id: <20230410141316.3317474-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230410141316.3317474-1-mchitale@ventanamicro.com> References: <20230410141316.3317474-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=mchitale@ventanamicro.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The state of smstateen0.FCSR bit impacts the execution of floating point instructions when misa.F==0. Add a field in the tb->flags which stores the current state of smstateen0.fcsr and will be used by floating point translation routines. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 5 +++++ target/riscv/translate.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 132cf06ff2..9c6b10d29a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -653,6 +653,7 @@ FIELD(TB_FLAGS, VTA, 24, 1) FIELD(TB_FLAGS, VMA, 25, 1) /* Native debug itrigger */ FIELD(TB_FLAGS, ITRIGGER, 26, 1) +FIELD(TB_FLAGS, FCSR, 27, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f88c503cf4..1590e6e480 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -117,6 +117,11 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, if (env->cur_pmbase != 0) { flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); } + if (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) { + flags = FIELD_DP32(flags, TB_FLAGS, FCSR, 1); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, FCSR, 0); + } *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0ee8ee147d..4880eaeb89 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -77,6 +77,7 @@ typedef struct DisasContext { int frm; RISCVMXL ol; bool virt_inst_excp; + bool smstateen_fcsr_ok; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; bool hlsx; @@ -1187,6 +1188,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; + ctx->smstateen_fcsr_ok = FIELD_EX32(tb_flags, TB_FLAGS, FCSR); } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)