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Thu, 30 Mar 2023 18:01:46 -0700 (PDT) Date: Fri, 31 Mar 2023 01:01:23 +0000 In-Reply-To: <20230331010131.1412571-1-komlodi@google.com> Mime-Version: 1.0 References: <20230331010131.1412571-1-komlodi@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230331010131.1412571-9-komlodi@google.com> Subject: [PATCH 08/16] hw/i3c/aspeed_i3c: Add IRQ MMIO behavior From: Joe Komlodi To: qemu-devel@nongnu.org Cc: venture@google.com, komlodi@google.com, peter.maydell@linaro.org Received-SPF: pass client-ip=2607:f8b0:4864:20::449; envelope-from=3-jAmZAcKCh0DHFEH6B9HH9E7.5HFJ7FN-67O7EGHG9GN.HK9@flex--komlodi.bounces.google.com; helo=mail-pf1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Hao Wu --- hw/i3c/aspeed_i3c.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index 2ed09234ff..b9aa1367d8 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -17,6 +17,8 @@ #include "qapi/error.h" #include "migration/vmstate.h" #include "trace.h" +#include "hw/i3c/i3c.h" +#include "hw/irq.h" /* I3C Controller Registers */ REG32(I3C1_REG0, 0x10) @@ -412,6 +414,46 @@ static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = { [R_SLAVE_CONFIG] = 0xffffffff, }; +static void aspeed_i3c_device_update_irq(AspeedI3CDevice *s) +{ + bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); + qemu_set_irq(s->irq, level); +} + +static uint32_t aspeed_i3c_device_intr_status_r(AspeedI3CDevice *s) +{ + /* Only return the status whose corresponding EN bits are set. */ + return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; +} + +static void aspeed_i3c_device_intr_status_w(AspeedI3CDevice *s, uint32_t val) +{ + /* INTR_STATUS[13:5] is w1c, other bits are RO. */ + val &= 0x3fe0; + s->regs[R_INTR_STATUS] &= ~val; + + aspeed_i3c_device_update_irq(s); +} + +static void aspeed_i3c_device_intr_status_en_w(AspeedI3CDevice *s, uint32_t val) +{ + s->regs[R_INTR_STATUS_EN] = val; + aspeed_i3c_device_update_irq(s); +} + +static void aspeed_i3c_device_intr_signal_en_w(AspeedI3CDevice *s, uint32_t val) +{ + s->regs[R_INTR_SIGNAL_EN] = val; + aspeed_i3c_device_update_irq(s); +} + +static void aspeed_i3c_device_intr_force_w(AspeedI3CDevice *s, uint32_t val) +{ + /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ + s->regs[R_INTR_STATUS] = val; + aspeed_i3c_device_update_irq(s); +} + static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, unsigned size) { @@ -426,6 +468,9 @@ static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, case R_INTR_FORCE: value = 0; break; + case R_INTR_STATUS: + value = aspeed_i3c_device_intr_status_r(s); + break; default: value = s->regs[addr]; break; @@ -470,6 +515,18 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset, break; case R_RESET_CTRL: break; + case R_INTR_STATUS: + aspeed_i3c_device_intr_status_w(s, val32); + break; + case R_INTR_STATUS_EN: + aspeed_i3c_device_intr_status_en_w(s, val32); + break; + case R_INTR_SIGNAL_EN: + aspeed_i3c_device_intr_signal_en_w(s, val32); + break; + case R_INTR_FORCE: + aspeed_i3c_device_intr_force_w(s, val32); + break; default: s->regs[addr] = val32; break;