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envelope-from=aaron@os.amperecomputing.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/cpu.h | 65 +++++++++++++++++++++++++++++++++-- target/arm/tcg/pauth_helper.c | 2 +- 2 files changed, 63 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f0f27f259d..868d844d5a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3705,18 +3705,77 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | - FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; + FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0 || + (id->id_aa64isar2 & + (FIELD_DP64(0, ID_AA64ISAR2, APA3, 0xf) | + FIELD_DP64(0, ID_AA64ISAR2, GPA3, 0xf))) != 0; } -static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) +static inline bool isar_feature_aa64_pauth_arch_qarma5(const ARMISARegisters *id) { /* - * Return true if pauth is enabled with the architected QARMA algorithm. + * Return true if pauth is enabled with the architected QARMA5 algorithm. * QEMU will always set APA+GPA to the same value. */ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; } +static inline bool isar_feature_aa64_pauth_arch_qarma3(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA3 algorithm. + * QEMU will always set APA3+GPA3 to the same result. + */ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0; +} + +static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) +{ + return isar_feature_aa64_pauth_arch_qarma5(id) || + isar_feature_aa64_pauth_arch_qarma3(id); +} + +static inline int isar_feature_pauth_get_features(const ARMISARegisters *id) +{ + if (isar_feature_aa64_pauth_arch_qarma5(id)) { + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA); + } else if (isar_feature_aa64_pauth_arch_qarma3(id)) { + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3); + } else { + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API); + } +} + +static inline bool isar_feature_aa64_pauth_epac(const ARMISARegisters *id) +{ + /* + * Note that unlike most AArch64 features, EPAC is treated (in the ARM + * psedocode, at least) as not being implemented by larger values of this + * field. Our usage of '>=' rather than '==' here causes our implementation + * of PAC logic to diverge from ARM pseudocode - we must check that + * isar_feature_aa64_pauth2() returns false AND + * isar_feature_aa64_pauth_epac() returns true, where the pseudocode reads + * as if EPAC is not implemented if the value of this register is > 0b10. + * See the implementation of pauth_addpac() for an example. + */ + return isar_feature_pauth_get_features(id) >= 0b0010; +} + +static inline bool isar_feature_aa64_pauth2(const ARMISARegisters *id) +{ + return isar_feature_pauth_get_features(id) >= 0b0011; +} + +static inline bool isar_feature_aa64_fpac(const ARMISARegisters *id) +{ + return isar_feature_pauth_get_features(id) >= 0b0100; +} + +static inline bool isar_feature_aa64_fpac_combine(const ARMISARegisters *id) +{ + return isar_feature_pauth_get_features(id) >= 0b0101; +} + static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 20f347332d..6bb3b5b9e5 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -282,7 +282,7 @@ static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier, static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, uint64_t modifier, ARMPACKey key) { - if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) { + if (cpu_isar_feature(aa64_pauth_arch_qarma5, env_archcpu(env))) { return pauth_computepac_architected(data, modifier, key); } else { return pauth_computepac_impdef(data, modifier, key);