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Tue, 14 Mar 2023 09:50:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions() Date: Tue, 14 Mar 2023 13:49:29 -0300 Message-Id: <20230314164948.539135-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In the near future, write_misa() will use a variation of what we have now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation will be required in write_misa() and it's already required here in riscv_cpu_realize(), so move it to riscv_cpu_validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a298e5e55..7458845fec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -916,6 +916,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) Error *local_err = NULL; uint32_t ext = 0; + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; + } + /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && @@ -1228,16 +1237,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } - - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu);