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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id t4-20020a056870e74400b0017293fa734asm675414oak.48.2023.03.02.22.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 22:51:05 -0800 (PST) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com, Anup Patel Subject: [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Date: Fri, 3 Mar 2023 12:20:54 +0530 Message-Id: <20230303065055.915652-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303065055.915652-1-mchitale@ventanamicro.com> References: <20230303065055.915652-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the callback for getting the architecture-dependent CPU ID ie mhartid. Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dd2f0c753..467d8467a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1243,6 +1243,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) } #ifndef CONFIG_USER_ONLY +static int64_t riscv_get_arch_id(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + + return cpu->env.mhartid; +} + #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps riscv_sysemu_ops = { @@ -1297,6 +1304,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->sysemu_ops = &riscv_sysemu_ops; + cc->get_arch_id = riscv_get_arch_id; #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;