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[92.224.150.4]) by smtp.gmail.com with ESMTPSA id s4-20020a1709062ec400b008f89953b761sm145895eji.3.2023.03.02.13.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 13:22:15 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Aurelien Jarno , Richard Henderson , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH v8 06/23] hw/isa/piix3: Move ISA bus IRQ assignments into host device Date: Thu, 2 Mar 2023 22:21:44 +0100 Message-Id: <20230302212201.224360-7-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230302212201.224360-1-shentey@gmail.com> References: <20230302212201.224360-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=shentey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Having the south bridge assign the ISA interrupts to the ISA bus itself makes the south bridge more self contained. Furthermore, it allows ISA interrupt wiring in pci_piix3_realize() which will be used in subsequent patches. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 6 +++--- hw/isa/piix3.c | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0295336d80..50a64f0326 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -246,10 +246,10 @@ static void pc_init1(MachineState *machine, object_property_set_bool(OBJECT(pci_dev), "smm-enabled", x86_machine_is_smm_enabled(x86ms), &error_abort); - pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); + piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), @@ -260,6 +260,7 @@ static void pc_init1(MachineState *machine, piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_register_input_irqs(isa_bus, x86ms->gsi); rtc_state = isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -268,7 +269,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } - isa_bus_register_input_irqs(isa_bus, x86ms->gsi); if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 27bd4dbf65..2e32a61647 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -302,6 +302,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); + isa_bus_register_input_irqs(isa_bus, d->pic); + i8257_dma_init(isa_bus, 0); /* RTC */