@@ -15,7 +15,6 @@
#include "migration/vmstate.h"
#include "net/net.h"
#include "net/eth.h"
-#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/net/lan9118.h"
#include "hw/ptimer.h"
@@ -32,12 +31,8 @@
#ifdef DEBUG_LAN9118
#define DPRINTF(fmt, ...) \
do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
-#define BADF(fmt, ...) \
-do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
#endif
/* The tx and rx fifo ports are a range of aliased 32-bit registers */
@@ -848,7 +843,8 @@ static uint32_t do_phy_read(lan9118_state *s, int reg)
case 30: /* Interrupt mask */
return s->phy_int_mask;
default:
- BADF("PHY read reg %d\n", reg);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "do_phy_read: PHY read reg %d\n", reg);
return 0;
}
}
@@ -876,7 +872,8 @@ static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
phy_update_irq(s);
break;
default:
- BADF("PHY write reg %d = 0x%04x\n", reg, val);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
}
}
@@ -1209,7 +1206,8 @@ static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
return;
}
- hw_error("lan9118_write: Bad size 0x%x\n", size);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "lan9118_16bit_mode_write: Bad size 0x%x\n", size);
}
static uint64_t lan9118_readl(void *opaque, hwaddr offset,
@@ -1324,7 +1322,8 @@ static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
return lan9118_readl(opaque, offset, size);
}
- hw_error("lan9118_read: Bad size 0x%x\n", size);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "lan9118_16bit_mode_read: Bad size 0x%x\n", size);
return 0;
}