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Thu, 16 Feb 2023 08:21:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v5 2/9] target/riscv: introduce riscv_cpu_cfg() Date: Thu, 16 Feb 2023 13:21:19 -0300 Message-Id: <20230216162126.809482-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230216162126.809482-1-dbarboza@ventanamicro.com> References: <20230216162126.809482-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We're going to do changes that requires accessing the RISCVCPUConfig struct from the RISCVCPU, having access only to a CPURISCVState 'env' pointer. Add a helper to make the code easier to read. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones --- target/riscv/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 01803a020d..368a522b5b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -653,6 +653,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) +static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env) +{ + return env_archcpu(env)->cfg; +} + #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else