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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 5/5] hw/riscv: Restrict CPU clusters to the expected type Date: Thu, 16 Feb 2023 15:23:38 +0100 Message-Id: <20230216142338.82982-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Microchip PolarFire SoC expects U51/U54 cores, the SiFive Freedom board: the E31/E51 and U34/U54. Do not allow any other CPU type by setting the cluster 'cpu-type' property. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 4 ++++ hw/riscv/sifive_u.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2b91e49561..658307fdfb 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -150,6 +150,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_E51); object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, TYPE_RISCV_HART_ARRAY); @@ -161,6 +163,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_U54); object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, TYPE_RISCV_HART_ARRAY); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d3ab7a9cda..d0535746ca 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -763,6 +763,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", SIFIVE_E_CPU); object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, TYPE_RISCV_HART_ARRAY); @@ -813,6 +814,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) * CPU must exist and have been parented into the cluster before the * cluster is realized. */ + qdev_prop_set_string(DEVICE(&s->u_cluster), "cpu-type", s->cpu_type); qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);