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[77.255.255.121]) by smtp.gmail.com with ESMTPSA id s1-20020a19ad41000000b004b7033da2d7sm141278lfd.128.2023.02.15.21.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 21:17:28 -0800 (PST) From: Marcin Nowakowski To: qemu-devel@nongnu.org Cc: marcin.nowakowski@fungible.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Richard Henderson Subject: [PATCH v2 1/4] target/mips: fix JALS32/J32 instruction handling for microMIPS Date: Thu, 16 Feb 2023 06:17:14 +0100 Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216051717.3911212-1-marcin.nowakowski@fungible.com> References: <20230216051717.3911212-1-marcin.nowakowski@fungible.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=marcin.nowakowski@fungible.com; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org microMIPS J & JAL instructions perform a jump in a 128MB region and 5 top bits of the address need to be preserved. This is different behavior compared to standard mips systems, where the jump is executed within a 256MB region. Note that microMIPS32 instruction set documentation appears to have inconsistent information regarding JALX32 instruction - it is written in the doc that: "To execute a procedure call within the current 256 MB-aligned region (...) The low 26 bits of the target address is the target field shifted left 2 bits." But the target address is already 26 bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 624e6b7786..567ca11ccf 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4917,6 +4917,13 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, break; case OPC_J: case OPC_JAL: + { + /* Jump to immediate */ + int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 : 0xF0000000; + btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) | + (uint32_t)offset; + break; + } case OPC_JALX: /* Jump to immediate */ btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |