Message ID | 20230215185726.691759-6-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | enable write_misa() and RISCV_FEATURE_* cleanups | expand |
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e34a5e3f11..4585ca74dc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -925,13 +925,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.pmp) { riscv_set_feature(env, RISCV_FEATURE_PMP); + } + + if (cpu->cfg.epmp) { + riscv_set_feature(env, RISCV_FEATURE_EPMP); /* * Enhanced PMP should only be available * on harts with PMP support */ - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); + if (!cpu->cfg.pmp) { + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } }