| Message ID | 20230214192356.319991-2-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | enable write_misa() and RISCV_FEATURE_* cleanups | expand |
On Wed, Feb 15, 2023 at 3:26 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > The masking done using env->misa_ext_mask already filters any extension > that QEMU doesn't support. If the hart supports the extension then QEMU > supports it as well. > > If the masking done by env->misa_ext_mask is somehow letting unsupported > QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead. > > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/csr.c | 3 --- > 1 file changed, 3 deletions(-) > Reviewed-by: Bin Meng <bmeng@tinylab.org>
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1693..e149b453da 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, /* Mask extensions that are not supported by this hart */ val &= env->misa_ext_mask; - /* Mask extensions that are not supported by QEMU */ - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ if ((val & RVD) && !(val & RVF)) { val &= ~RVD;