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[77.13.82.236]) by smtp.gmail.com with ESMTPSA id c10-20020a056402100a00b00483dd234ac6sm8178318edu.96.2023.01.31.03.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 03:53:58 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Igor Mammedov , Richard Henderson , Ani Sinha , "Michael S. Tsirkin" , Paolo Bonzini , BALATON Zoltan , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Laurent Vivier , Sunil Muthuswamy , qemu-trivial@nongnu.org, Bernhard Beschow Subject: [PATCH v2 09/20] hw/isa/lpc_ich9: Unexport PIRQ functions Date: Tue, 31 Jan 2023 12:53:15 +0100 Message-Id: <20230131115326.12454-10-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131115326.12454-1-shentey@gmail.com> References: <20230131115326.12454-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org No need to rely on the board to wire up the ICH9 PCI IRQs. All functions access private state of the LPC device which suggests that it should wire up the IRQs. Signed-off-by: Bernhard Beschow --- include/hw/i386/ich9.h | 3 --- hw/i386/pc_q35.c | 3 --- hw/isa/lpc_ich9.c | 11 ++++++++--- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 36e0ccd16a..921e4c7ef6 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -9,9 +9,6 @@ #include "hw/acpi/ich9.h" #include "qom/object.h" -void ich9_lpc_set_irq(void *opaque, int irq_num, int level); -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled); I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 50fa5aa9bc..83e4fb7868 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -267,9 +267,6 @@ static void pc_q35_init(MachineState *machine) for (i = 0; i < GSI_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } - pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); - pci_bus_map_irqs(host_bus, ich9_lpc_map_irq); - pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8d541e2b54..b444faacd2 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -259,7 +259,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) qemu_set_irq(lpc->gsi[gsi], level); } -void ich9_lpc_set_irq(void *opaque, int pirq, int level) +static void ich9_lpc_set_irq(void *opaque, int pirq, int level) { ICH9LPCState *lpc = opaque; int pic_irq, pic_dis; @@ -275,7 +275,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level) /* return the pirq number (PIRQ[A-H]:0-7) corresponding to * a given device irq pin. */ -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) +static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) { BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); PCIBus *pci_bus = PCI_BUS(bus); @@ -286,7 +286,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; } -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) +static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) { ICH9LPCState *lpc = opaque; PCIINTxRoute route; @@ -680,6 +680,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) { ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); DeviceState *dev = DEVICE(d); + PCIBus *pci_bus = pci_get_bus(d); ISABus *isa_bus; if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) && @@ -728,6 +729,10 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, lpc->gsi); i8257_dma_init(isa_bus, 0); + + pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); + pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); + pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); } static bool ich9_rst_cnt_needed(void *opaque)