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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id kw4-20020a170907770400b0084d397e0938sm19670453ejc.195.2023.01.22.09.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Jan 2023 09:07:46 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ani Sinha , "Michael S. Tsirkin" , Aurelien Jarno , Bernhard Beschow Subject: [PATCH 5/7] hw/acpi/piix4: Fix offset of GPE0 registers Date: Sun, 22 Jan 2023 18:07:22 +0100 Message-Id: <20230122170724.21868-6-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230122170724.21868-1-shentey@gmail.com> References: <20230122170724.21868-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The PIIX4 datasheet defines the GPSTS register to be at offset 0x0c of the power management I/O register block. This register block is represented in the device model by the io attribute. So make io_gpe a child memory region of io at offset 0x0c. Note that SeaBIOS sets the base address of the register block to 0x600, resulting in the io_gpe block to start at 0x60c. GPE_BASE is defined as 0xafe0 which is 0xa9d4 bytes off. In order to preserve compatibilty, create an io_gpe_qemu memory region alias at GPE_BASE. Signed-off-by: Bernhard Beschow --- include/hw/acpi/piix4.h | 1 + hw/acpi/piix4.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h index 62e1925a1f..4e6cad9e8c 100644 --- a/include/hw/acpi/piix4.h +++ b/include/hw/acpi/piix4.h @@ -40,6 +40,7 @@ struct PIIX4PMState { MemoryRegion io; MemoryRegion io_gpe; + MemoryRegion io_gpe_qemu; ACPIREGS ar; APMState apm; diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 2e9bc63fca..836f9026b1 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -49,6 +49,7 @@ #include "qom/object.h" #define GPE_BASE 0xafe0 +#define GPE_OFS 0xc #define GPE_LEN 4 #define ACPI_PCIHP_ADDR_PIIX4 0xae00 @@ -429,7 +430,7 @@ static void piix4_pm_add_properties(PIIX4PMState *s) object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, &acpi_disable_cmd, OBJ_PROP_FLAG_READ); object_property_add_uint64_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, - &s->io_gpe.addr, OBJ_PROP_FLAG_READ); + &s->io_gpe_qemu.addr, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, &s->ar.gpe.len, OBJ_PROP_FLAG_READ); object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, @@ -558,7 +559,11 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, { memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, "acpi-gpe0", GPE_LEN); - memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); + memory_region_add_subregion(&s->io, GPE_OFS, &s->io_gpe); + + memory_region_init_alias(&s->io_gpe_qemu, OBJECT(s), "acpi-gpe0-qemu", + &s->io_gpe, 0, memory_region_size(&s->io_gpe)); + memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe_qemu); if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) { acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,