From patchwork Tue Dec 20 22:04:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabiano Rosas X-Patchwork-Id: 1718047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=suse.de header.i=@suse.de header.a=rsa-sha256 header.s=susede2_rsa header.b=ZjFyKStg; dkim=pass header.d=suse.de header.i=@suse.de header.a=ed25519-sha256 header.s=susede2_ed25519 header.b=TuAuMyq4; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Nc9gv4rndz1ydd for ; Wed, 21 Dec 2022 09:08:27 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p7klJ-0006no-8a; Tue, 20 Dec 2022 17:07:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p7klA-0006n9-VG; Tue, 20 Dec 2022 17:06:52 -0500 Received: from smtp-out2.suse.de ([2001:67c:2178:6::1d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p7kl8-0006fG-Og; Tue, 20 Dec 2022 17:06:52 -0500 Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 6B18D76A4A; Tue, 20 Dec 2022 22:06:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1671574008; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uNooRhtg57jwueZDg2HkPFfIvQcQ1FUxw6N+xDzNzjc=; b=ZjFyKStgZIG4w5VtecSY3HY3t9sRva9i42R+iLExDXf5Ge541G4aYWgDPUZ+Ica3gIkwO3 ANNN9WB69k5CjVd+12IXJVUoRwO29FMSLVgqtrtjSGMfh28NPVFwACHsbwZ1CGsaWPRcZ+ VkQV1yMFpfHVof420vQ6tSdTkmQXN0U= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671574008; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uNooRhtg57jwueZDg2HkPFfIvQcQ1FUxw6N+xDzNzjc=; b=TuAuMyq4RMxDU16RnMD4lEl3MXZ/wY2Bf/g1rc5eZD43TkTx4JbRGya1qPGdmLK8PCjAlX HJx48XYDxxFnwoAQ== Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 847BB13254; Tue, 20 Dec 2022 22:06:45 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id IKAtEvUxomPwfAAAMHmgww (envelope-from ); Tue, 20 Dec 2022 22:06:45 +0000 From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH v2 5/5] target/arm: only perform TCG cpu and machine inits if TCG enabled Date: Tue, 20 Dec 2022 19:04:26 -0300 Message-Id: <20221220220426.8827-6-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221220220426.8827-1-farosas@suse.de> References: <20221220220426.8827-1-farosas@suse.de> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Claudio Fontana of note, cpreg lists were previously initialized by TCG first, and then thrown away and replaced with the data coming from KVM. Now we just initialize once, either for TCG or for KVM. Signed-off-by: Claudio Fontana [moved arm_cpu_register_gdb_regs_for_features out of tcg_enabled] Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Richard Henderson --- Originally from: [RFC v14 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled https://lore.kernel.org/r/20210416162824.25131-17-cfontana@suse.de --- target/arm/cpu.c | 31 +++++++++++++++++------------- target/arm/kvm.c | 18 +++++++++--------- target/arm/kvm_arm.h | 3 +-- target/arm/machine.c | 45 +++++++++++++++++++++++++------------------- 4 files changed, 54 insertions(+), 43 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2fa022f62b..fdf30e7268 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -525,9 +525,11 @@ static void arm_cpu_reset_hold(Object *obj) } #endif - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); - arm_rebuild_hflags(env); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); + } } #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) @@ -1600,6 +1602,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } } +#ifdef CONFIG_TCG { uint64_t scale; @@ -1625,7 +1628,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, arm_gt_hvtimer_cb, cpu); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { @@ -1943,17 +1947,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - pmu_init(cpu); - - if (!kvm_enabled()) { + if (tcg_enabled()) { + pmu_init(cpu); arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); - } #ifndef CONFIG_USER_ONLY - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, - cpu); + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, + cpu); #endif + } } else { cpu->isar.id_aa64dfr0 = FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); @@ -2049,10 +2052,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_VBAR); } - register_cp_regs_for_features(cpu); - arm_cpu_register_gdb_regs_for_features(cpu); + if (tcg_enabled()) { + register_cp_regs_for_features(cpu); + init_cpreg_list(cpu); + } - init_cpreg_list(cpu); + arm_cpu_register_gdb_regs_for_features(cpu); #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2..2f01c26f54 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -438,9 +438,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } -/* Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). +/* + * Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about. + * + * The parallel for TCG is init_cpreg_list() */ int kvm_arm_init_cpreg_list(ARMCPU *cpu) { @@ -482,12 +484,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) arraylen++; } - cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); - cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); - cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, - arraylen); - cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, - arraylen); + cpu->cpreg_indexes = g_new(uint64_t, arraylen); + cpu->cpreg_values = g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); cpu->cpreg_array_len = arraylen; cpu->cpreg_vmstate_array_len = arraylen; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 99017b635c..41de2a7cf1 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -70,8 +70,7 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, * @cpu: ARMCPU * * Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). + * definition of what CPU registers it knows about. * * Returns: 0 if success, else < 0 error code */ diff --git a/target/arm/machine.c b/target/arm/machine.c index a186787d2b..5ac1e6173a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" @@ -687,7 +688,7 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu = opaque; - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } @@ -722,7 +723,7 @@ static int cpu_post_save(void *opaque) { ARMCPU *cpu = opaque; - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_finish(&cpu->env); } @@ -741,7 +742,7 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state = UINT32_MAX; - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } @@ -820,27 +821,28 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); - /* - * TCG gen_update_fp_context() relies on the invariant that - * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; - * forbid bogus incoming data with some other value. - */ - if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { - if (extract32(env->v7m.fpdscr[M_REG_NS], - FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || - extract32(env->v7m.fpdscr[M_REG_S], - FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { - return -1; + /* + * TCG gen_update_fp_context() relies on the invariant that + * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; + * forbid bogus incoming data with some other value. + */ + if (arm_feature(env, ARM_FEATURE_M) && + cpu_isar_feature(aa32_lob, cpu)) { + if (extract32(env->v7m.fpdscr[M_REG_NS], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || + extract32(env->v7m.fpdscr[M_REG_S], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { + return -1; + } } - } - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); + arm_rebuild_hflags(&cpu->env); } - arm_rebuild_hflags(&cpu->env); return 0; } @@ -890,8 +892,13 @@ const VMStateDescription vmstate_arm_cpu = { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), +#ifdef CONFIG_TCG VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), +#else + VMSTATE_UNUSED(sizeof(QEMUTimer *)), + VMSTATE_UNUSED(sizeof(QEMUTimer *)), +#endif /* CONFIG_TCG */ { .name = "power_state", .version_id = 0,