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Tue, 20 Dec 2022 03:34:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Thomas Huth , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 4/7] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property Date: Tue, 20 Dec 2022 12:34:33 +0100 Message-Id: <20221220113436.14299-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220113436.14299-1-philmd@linaro.org> References: <20221220113436.14299-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé This device does not have to be TARGET-dependent. Add a 'cpu_big_endian' property which sets the byte-swapping options if required. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221209151533.69516-5-philmd@linaro.org> Reviewed-by: Richard Henderson --- hw/mips/gt64xxx_pci.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index f6fa309ef7..4cafc76a23 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "qemu/log.h" +#include "hw/qdev-properties.h" #include "hw/registerfields.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" @@ -256,6 +257,9 @@ struct GT64120State { PCI_MAPPING_ENTRY(ISD); MemoryRegion pci0_mem; AddressSpace pci0_mem_as; + + /* properties */ + bool cpu_little_endian; }; /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -998,16 +1002,11 @@ static const MemoryRegionOps isd_mem_ops = { static void gt64120_reset(DeviceState *dev) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); -#if TARGET_BIG_ENDIAN - bool cpu_little_endian = false; -#else - bool cpu_little_endian = true; -#endif /* FIXME: Malta specific hw assumptions ahead */ /* CPU Configuration */ - s->regs[GT_CPU] = cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0; + s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0; s->regs[GT_MULTI] = 0x00000003; /* CPU Address decode */ @@ -1114,7 +1113,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_TC_CONTROL] = 0x00000000; /* PCI Internal */ - s->regs[GT_PCI0_CMD] = cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0; + s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0; s->regs[GT_PCI0_TOR] = 0x0000070f; s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; @@ -1131,7 +1130,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; - s->regs[GT_PCI1_CMD] = cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0; + s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0; s->regs[GT_PCI1_TOR] = 0x0000070f; s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; @@ -1224,11 +1223,18 @@ static const TypeInfo gt64120_pci_info = { }, }; +static Property gt64120_properties[] = { + DEFINE_PROP_BOOL("cpu-little-endian", GT64120State, + cpu_little_endian, !TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + static void gt64120_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + device_class_set_props(dc, gt64120_properties); dc->realize = gt64120_realize; dc->reset = gt64120_reset; dc->vmsd = &vmstate_gt64120;