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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:52 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 19/32] hw/isa/piix3: Rename typedef PIIX3State to PIIXState Date: Sun, 4 Dec 2022 20:05:40 +0100 Message-Id: <20221204190553.3274-20-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-25-shentey@gmail.com> --- hw/isa/piix3.c | 50 +++++++++++++++++------------------ include/hw/southbridge/piix.h | 4 +-- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7faa699a3d..ff349c99ad 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -38,7 +38,7 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & @@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) piix3->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; @@ -77,7 +77,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } @@ -94,7 +94,7 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; @@ -109,7 +109,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus = pci_get_bus(&piix3->dev); int pirq; @@ -125,7 +125,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); int pic_irq; pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -158,7 +158,7 @@ static void piix3_write_config_xen(PCIDevice *dev, static void piix_reset(DeviceState *dev) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; /* master, memory and I/O */ @@ -199,7 +199,7 @@ static void piix_reset(DeviceState *dev) static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int pirq; /* @@ -222,7 +222,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] = @@ -234,7 +234,7 @@ static int piix3_pre_save(void *opaque) static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; return (piix3->rcr != 0); } @@ -245,7 +245,7 @@ static const VMStateDescription vmstate_piix3_rcr = { .minimum_version_id = 1, .needed = piix3_rcr_needed, .fields = (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -257,8 +257,8 @@ static const VMStateDescription vmstate_piix3 = { .post_load = piix3_post_load, .pre_save = piix3_pre_save, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -271,7 +271,7 @@ static const VMStateDescription vmstate_piix3 = { static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -282,7 +282,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; return d->rcr; } @@ -299,7 +299,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -385,7 +385,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) static void pci_piix3_init(Object *obj) { - PIIX3State *d = PIIX3_PCI_DEVICE(obj); + PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); @@ -393,10 +393,10 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -426,7 +426,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX3State), + .instance_size = sizeof(PIIXState), .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, @@ -440,7 +440,7 @@ static const TypeInfo piix3_pci_type_info = { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); @@ -470,7 +470,7 @@ static const TypeInfo piix3_info = { static void piix3_xen_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 39c31da9ad..a489f52d1b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -72,10 +72,10 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; +typedef struct PIIXState PIIXState; #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, +DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) #define TYPE_PIIX3_DEVICE "PIIX3"