From patchwork Tue Nov 1 00:58:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 1697590 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=daynix-com.20210112.gappssmtp.com header.i=@daynix-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=0q4okmsU; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N1Wwy0TWQz23l6 for ; Tue, 1 Nov 2022 12:03:30 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opfdK-0004c5-PJ; Mon, 31 Oct 2022 21:00:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opfd6-0004P6-DP for qemu-devel@nongnu.org; Mon, 31 Oct 2022 20:59:51 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opfd3-0005wm-Io for qemu-devel@nongnu.org; Mon, 31 Oct 2022 20:59:47 -0400 Received: by mail-pj1-x102d.google.com with SMTP id l22-20020a17090a3f1600b00212fbbcfb78so17445815pjc.3 for ; Mon, 31 Oct 2022 17:59:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r10TkuBoyEwvau/bgUnLf5IBkvgqqBcYI2/YSx6NHxc=; b=0q4okmsU8objBLDM4s21b4ZX1OwJaVSOXamrUEaPOvhz8AlOppaIl9UU32adXVebc0 onDEToOliTaq7cEbkEcazumkXYIC18eYSCvJy+qIv6c3Zech9Uju1LjcgGzSa+jSoWb1 eNclF3ItRumc8zMiNL5lG84GkZgvtla5m8/0zG1sR8KeyUCAbrSuwl9vPChq5bjrgj7Q ttzkETHrGl8RrsxFGbObr6AC3Un5f8w/CIo2mW+uWWMTzbVqAWUbtREwjZfUUWM/fyOQ gBJdJykDSNjf8XgyoIqAgiRBTv1yEIHhePo2TOoA3SpgBAtcTJuipiToK/KtCfjmNc7t dLiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r10TkuBoyEwvau/bgUnLf5IBkvgqqBcYI2/YSx6NHxc=; b=8J8LVkIKhmhHey9nUN/ASAih8eg7UNJVtDDqIwZO94ErOYlsLsp6QO/V+MJ4GAv+9F MTeMbJqEP57HKUWkStH9FGEyGLoGxHU3LAHDSUFgN8DEpCR4pPHWxjWbW/Wx5JFlVxLI FzJIBueapIxFahcpyt7RXAzBHfGyi50wp68PbPbqFB//pqZx4AGQ3aOo9vncz/ap3Tn/ Y8N0mvtsFvxdPRejlY8cZnjlYq+GUBmJbWhGstL6bWJjIiAwltVDFWAX/YB1X+GhTznk IHls0B9dS/dbKOMI0eYmLMKcLFdOR582UIGtGJaHS5Egt5MyWDcq+8k4O81OpQxeAaVK 6Cmg== X-Gm-Message-State: ACrzQf29dblkn5lMcGcf8mTooKBDfnQQUgmAX96/bkVJliezuZZtiW9T 7ngv2FZ/5R52QJfHXUMcbwajlN8XhwBzmqCJ X-Google-Smtp-Source: AMsMyM4FBkGznuO4wnO2oFj9JuGTNLHdhQW5K3XCME3cdHKg5Hd5B2bpyZjRp0nhh7hzRx3wrz/5QQ== X-Received: by 2002:a17:902:900a:b0:178:77c7:aa28 with SMTP id a10-20020a170902900a00b0017877c7aa28mr16592571plp.3.1667264384071; Mon, 31 Oct 2022 17:59:44 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id o9-20020aa79789000000b0056d98e359a5sm1875644pfp.165.2022.10.31.17.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 17:59:43 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v7 07/17] hw/nvme: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 09:58:49 +0900 Message-Id: <20221101005859.4198-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101005859.4198-1-akihiko.odaki@daynix.com> References: <20221101005859.4198-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/nvme/ctrl.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 87aeba0564..ff4e2beea6 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7325,17 +7325,9 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset) PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); } -static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) +static void nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) { - Error *err = NULL; - int ret; - - ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &err); - if (err) { - error_report_err(err); - return ret; - } + pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); pci_set_word(pci_dev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_2); @@ -7343,8 +7335,6 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) PCI_PM_CTRL_NO_SOFT_RESET); pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_STATE_MASK); - - return 0; } static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)