From patchwork Tue Nov 1 00:58:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 1697589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=daynix-com.20210112.gappssmtp.com header.i=@daynix-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=7S0Qny8L; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N1Www0Cq3z23l6 for ; Tue, 1 Nov 2022 12:03:28 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opfes-0006KW-52; Mon, 31 Oct 2022 21:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opfdn-0004qt-2N for qemu-devel@nongnu.org; Mon, 31 Oct 2022 21:00:33 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opfdj-0006e3-8q for qemu-devel@nongnu.org; Mon, 31 Oct 2022 21:00:29 -0400 Received: by mail-pl1-x62c.google.com with SMTP id l2so12199810pld.13 for ; Mon, 31 Oct 2022 18:00:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HE9eNBY7g78il39owcm9+qENzxyBHsC1WY0V/xnA/n4=; b=7S0Qny8LAsoDGYn18UFJxdivyXaKR6cuxI3yy+Uo2AB/Z8TvguzbIkGNcrMF+VDd8L cf92eJsPB0mNWO7kQt6gh7L1EhPHZQ4xKODvVTy9+EzopDnqpKPz4CD69awm39DcSJai ahdSvb8o3usa8MV91WtXonbkncYNc6HdnK8l/TjWH3r8Eqjsxwqz+U7txiVFE/9V/u4C 9tTUvW62fmSv9n6eafuU+TNl/x0+aRxY8R9hmn9/ohLxa4Lv+20Rc6GA19w/pUb6w8uJ yAOur0OKHaedbC0LWHIGPvtMokRjra0Uc3dSYev/ch78HmPzjmvcHp4yR0/ft0/vlJMd RYGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HE9eNBY7g78il39owcm9+qENzxyBHsC1WY0V/xnA/n4=; b=DKA3asJFHvcmXu+snEGo3UQqJvWzcFWhedjdj5dWZSob9Wr8NkuR/q/PZ3SFefMu3a RRr0ZajcFvQiXCRtfktnq59IGjeLoBS5H4fzyBT645eVEK7L/tSavdbp3ZSBVMUDTl/i qZwK8FYzqn+K+fk4cCdpUa/DPkZEkHgWVSQxuPE3tNBZptZktxdE5QoNFAoTPF590m1f INPo2+QtxTIan9G/Qn9DKnl1vFtdVeTIGuEwTHmo7rbZKjqeGdfOZTyZV43TIDDjadeM Tm0X8P5FD5jgvd44SldzTL0wjYIys57OE7XuEwBRfHP4Q+chrDX7Z6M9yPY/Q5V0F+Y1 mvWQ== X-Gm-Message-State: ACrzQf24OCD7yBxR1uRRkgKKPAg4pLWQyINV/NyL1jjAXafpsfW1EXJj RJIE/obpeGbsMabZdxnqOe1JpUYB3FbWiTty X-Google-Smtp-Source: AMsMyM4jI/itT7IuRrr+ojtPFE0bKU+0ofZwxxknMIADDumbvROM4zldhbbccYNJGSgouiZv16bBxQ== X-Received: by 2002:a17:902:e5cb:b0:187:2d8c:a4fa with SMTP id u11-20020a170902e5cb00b001872d8ca4famr4244426plf.151.1667264424843; Mon, 31 Oct 2022 18:00:24 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id o9-20020aa79789000000b0056d98e359a5sm1875644pfp.165.2022.10.31.18.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 18:00:24 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v7 15/17] hw/vfio/pci: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 09:58:57 +0900 Message-Id: <20221101005859.4198-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101005859.4198-1-akihiko.odaki@daynix.com> References: <20221101005859.4198-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::62c; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org The code generating errors in pci_add_capability has a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, in pci_add_capability(), we can always assert that capabilities never overlap, and that is what happens when omitting errp. Signed-off-by: Akihiko Odaki --- hw/vfio/pci-quirks.c | 15 +++------------ hw/vfio/pci.c | 14 +++++--------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f0147a050a..e94fd273ea 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1530,7 +1530,7 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique = { static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) { PCIDevice *pdev = &vdev->pdev; - int ret, pos = 0xC8; + int pos = 0xC8; if (vdev->nv_gpudirect_clique == 0xFF) { return 0; @@ -1547,11 +1547,7 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) return -EINVAL; } - ret = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: "); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8); memset(vdev->emulated_config_bits + pos, 0xFF, 8); pos += PCI_CAP_FLAGS; @@ -1718,12 +1714,7 @@ static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp) return -EFAULT; } - ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, - VMD_SHADOW_CAP_LEN, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: "); - return ret; - } + pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, VMD_SHADOW_CAP_LEN); memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); pos += PCI_CAP_FLAGS; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 7ef1044f22..bd639a8fbb 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1839,7 +1839,7 @@ static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); } -static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, +static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, uint8_t pos, uint8_t size, Error **errp) { uint16_t flags; @@ -1956,11 +1956,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1, PCI_EXP_FLAGS_VERS); } - pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, - errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); vdev->pdev.exp.exp_cap = pos; @@ -2058,14 +2054,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap = pos; - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; default: - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; }